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程序功能为从两个外部并行端口读取16位数据,16位数据在8个模拟时钟的控制下被转换为串行数据从51单片机的P2.3、P2.6读取。
主程序分16次读取32个字节数据。-The program features 16-bit data read from two external parallel port, 16-bit data is converted to 8 analog clock under the control of the serial data from the micr
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串行转并行算法,自己编写,已经运行成功,算法简单易懂。-Serial to parallel algorithm
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AT89C52单片机整体介绍,包含指令系统,汇编语言程序设计,中断,定时器计数器,串并扩展和人机交互-AT89C52 microcontroller overall, including instruction, assembly language programming, interrupt, timer counter, serial-to-parallel extension and human-computer interaction
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在做一个项目应用时,使用的I/O较多,应用到了74595来做扩展,但是若要挂接多片74595,势必也要多用到I/O口,为了解决这个问题,我将每2片74595做级联,然后再将级联之后的所有时钟线与数据再并联在一起(即所有的74595共用时钟与数据线,故只占用2个I/O口线),最后对每一组的锁存控制线做单独控制(在这里也相当于片选了),这样一来硬件电路得到了很大程度的简化,同时在程序上也可以共用一个74595的驱动子程序,控制不同的锁存控制线,串行数据也就送到了不同74595级联模组端口。故此对硬件
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NOTE THAT THE DESCRAMBLE ROUTINE IS IDENTICAL TO THE SCRAMBLE ROUTINE
this routine implements the serial descrambling algorithm in parallel form
this advances the lfsr 8 bits every time it is called
this uses fewer than 25 xor gates to imple
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this routine implements the serial descrambling algorithm in parallel form
for the LSFR polynomial: x^16+x^5+x^4+x^3+1
this advances the LSFR 8 bits every time it is called
this requires fewer than 25 xor gates to implement (with a stati
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加法器
输入信号:
输入数实部Ra,Rb,Rc,Rd,虚部Ia,Ib,Ic,Id的数据宽度均为19位;每次向加法器阵列只能送一个操作数,包括实数R(19bit)、虚部I(19bit);操作数据a、c、b、d的顺序连续送入,在加法器列中要进行串并变换。
CP脉冲。
输出信号:
输出数实部Ra’,Rb’,Rc’,Rd’,虚部Ia’,Ib’,Ic’,Id’的数据宽度均为21位。-Adder input signal: the real part of the input numbe
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RDH2159 PCI转串并口驱动,支持vista、xp、2000、98系统,目前还不能够支持win7,有详细的安装说明,亲自测试能够安装使用。-RDH2159 PCI serial and parallel transfer driver support vista, xp, 2000,98 system is not currently able to support win7, there are detailed installation instructions, personally
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12864 液晶屏显示代码,实现两种控制方式,串行引脚控制,并行IO控制,AVR源代码-12864 LCD display code to achieve two control modes, the serial pin control, parallel IO control, AVR source code
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The MSP430 micros have JTAG interface that allows access to the internal bus of the processor to locate breakpoints (breakpoints), analyze the values of the variables in memory and run the program instruction by instruction. This interf
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基于MSP430G2553的12864液晶串行、四位和八位并行显示字符、图片等程序,用的是5V液晶,注意电路的连接。-The 12864-based LCD MSP430G2553 serial, four and eight parallel display characters, pictures and other procedures, using a 5V LCD, pay attention to the circuit connection.
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基于C8051F340的SD卡读写,移植了FATFS的文件系统。可以实现文件的读写...[sd卡(驱动)工作原理分析完整版.rar] - 1硬件初始化,与CPU相关的配置,SSIO...
-he 2828 supports up to 1Gbps per lane speed with
maximum 4 lanes using both parallel RGB interface and serial SPI interface
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LU_seial,c是针对c语言开发的串行LU分解,并进行了cache优化。
LU_parallel.c是用多线程的方法实现LU分解的并行化,加速比在1.3左右。-LU_seial, c is for c language development serial LU decomposition, and conducted cache optimization. LU_parallel.c is multi-threaded approach to achieve parallel LU d
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无人机任务转发功能板源码,基于AT89C2051,通过串口接收任务指令,并口输出给主控-UAVs forwarding board source, based on AT89C2051, task instructions received through the serial port, parallel port output to the master
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通过51单片机串行转并行,扩展IO口,实现四个步进电动机的控制。-By 51 microcontroller serial to parallel IO expansion port, to achieve four stepper motor control.
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DDS:AD9850的单片机控制资料,包含了串行和并行数据输入的代码,下载文件在HEX文件夹中。-DDS: AD9850 single-chip control information, including serial and parallel data input of the code to download the file in HEX folder.
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VB获取计算机所有串口、并口的端口地址,很好的参考。-VB to get all of your computer serial port, parallel port address, a good reference.
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The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the outpu
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fpga的基于verilog的串行数据转并行数据的相关资料,相关内容uart协议,串并转换程序-verilog fpga-based serial data to parallel data, relevant information, relevant content uart protocol string and conversion program
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Write a HDL Code to use as a serial to parallel converter
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