搜索资源列表
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
FIR
- Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
Crack_QII70
- Quartus II 7.0 crack
ff
- QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。-QUARTUS II platform based on the VHDL language elevator system control procedures.
Execise
- altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
16bit_display8bitLED
- Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
elecfans.com_quargfjc1105
- QUARTUS II的经典教程，可以快速学会QUARTUS II的一些基础应用-Tutorial QUARTUS II classic, can quickly learn to QUARTUS II of the application of some basic
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
The-Duck
- Crack for Quartus II 8.0
DE2_NIOS_HOST_MOUSE_VGA
- 在ALTERA的DE2开发板上做的关于HOST_MOUSE的例子，基于Quartus II 和SOPC Builder以及Nios II IDE平台所完成！-ALTERA development in the DE2 board to do on HOST_MOUSE example, based on the Quartus II and SOPC Builder and Nios II IDE platform completed!
DE2_SD_Card_Audio
- 在ALTERA的DE2板子上做的一个读写SD卡的例子，基于QUARTUS II ,SOPC BUILDER ,Nios II IDE实现的，从SD卡读写东西-The DE2 board in ALTERA do an SD card reader example, based on the QUARTUS II, SOPC BUILDER, Nios II IDE achieved something from the SD card reader
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
AlteraFPGA
- quartus II 软件入门和进阶，是《ALtera fpga_cpld 设计》（基础篇）-quartus II software, introductory and advanced, is " ALtera fpga_cpld design" (Basics)
Crack_patch_license
- Quartus II 6.0 破解补丁和license设置-Quartus II 6.0 crack patch and license settings
sdramtEST
- sdram动态存储器测试的源文件工程，Quartus II 9.0 (32-Bit)版本。-sdram TEST
Quartus-II-Handbook_72
- QuartusII7.2的用户手册，英文-QuartusII7.2 user manual, English
Crack_QII10.0_x86
- Quartus II 10.0_x86版破解补丁，此补丁在Windows XP和Windows 7的32/64位操作系统下都验证过了，都能使软件流畅运行-Quartus II 10.0_x86 Edition crack patch, this patch in Windows XP and Windows 7, 32/64 bit operating systems are verified, and can make the software run smoothly
sinbo
- 基于quartus II的正弦波发生器，可调频率相位，用其时序仿真即可显示，分模块设计的。有sin。mif文件.-Based quartus II of the sine wave generator, adjustable frequency and phase, with the timing simulation can show that sub-module design. A sin. mif file.
Crack_Quartus+II+9.1
- Its crack file for Altera Quartus 9.1