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08-1_VGA_Display_Test_640480
- 基于quartusII开发环境的VGA视频通信程序，很好的资料，欢迎下载-Based on quartusII development environment of VGA video communication program, very good information, welcome to download
09_SDRAM_VGA_Display_Test640480
- 在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design
shudianbaogao
- 在Multisim和QuartusII中实现数字频率计的Word论文-Multisim and QuartusII
High_Speed_Samples
- 在QUARTUSII中使用verilog实现基于FPGA的高速数字采样器。-The use of Verilog in QUARTUSII in the realization of high speed digital sampler based on FPGA.
led_book
- 通过FPGA实现LED点阵效果的显示。使用quartusii平台，verilog编程-Through LED to achieve the display of FPGA matrix effect. Using QuartusII platform, Verilog programming
license
- Altera QuartusII V15.0
beep
- 基于quartusii 设计fpga蜂鸣器实验,检测蜂鸣器是否正常工作，-Based quartusii design fpga buzzer experiments, testing the buzzer is working,
VGA_pic_200x200x3(ok)
- altera 系列FPGA实现的VGA显示8色的图片，调试通过，开发环境quartusii , 语言verilog。-Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过 ， 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
zy1
- 基于quartusII利用VHDL语言实现逻辑与门的仿真并分析延时的影响-Based on quartusII using VHDL language to achieve logic and gate simulation and analysis of the impact of delay
zy2
- 基于quartusII利用VHDL语言实现数据选择器的仿真并分析延时的影响-Based on quartusII using VHDL language to achieve data selector simulation and analysis of the impact of delay
Qsys学习入门
- 学习altera qsys编程的必备学习资料(Learning Altera qsys programming essential learning materials)
RS232
- 基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)
source code
- 2.6'TFT_LCD驱动源程序，可以在quartusII平台上直接运行(2.6'TFT_LCD driver source program, you can run directly on the quartus II platform)
jiou
- 实现奇偶校验，根据波形仿真检测序列的奇偶(Implementing sequence parity check)
QuartusII
- FPGA中实现FFT的计算，实现频率信息的获取和识别，非常好用(FPGA implementation of FFT calculation, frequency information acquisition and identification, very useful)
wannianli
- 2、 掌握QuartusII软件的使用； 3、 掌握计数器的设计； 4、 掌握分频器的设计； 5、 掌握时、分、秒的设计； 6、 数码管的扫描显示； 7、 掌握数字钟的整体设计(2, master the use of QuartusII software; 3. Master the design of the counter; 4. Master the design of frequency divider; 5, mastering the design of time,
fifo
- 每一个时钟（clk_100m）上升沿，判断写请求信号是否为高电平，如果为高电平，那么就将数据线上的数据写入FIFO，然后在下一个时钟上升沿，wrf_use增加1，表示FIFO队列里的数据增加了一个。 细心的朋友可能会发现，其实在这一过程中，读请求信号一直为高电平，仔细分析这两张图片，大概可以得出如下判断： 在每个读时钟的上升沿，首先判断读请求信号是否为高电平，若为高电平，再判断FIFO是否为空，如果不为空，那么在下一个read_clock的上升沿将数据读出(us QuartusII desi
SOPC开发快速入门教程中文版
- 本文为基于QuartusII和NiosII IDE的FPGA/SOPC开发资料，目的是为了尽快掌握FPGA/SOPC的开发流程，投入实践当中。(This paper develops data for FPGA/SOPC based on QuartusII and NiosII IDE. The purpose is to master the development process of FPGA/SOPC as soon as possible and put into practice.
sandclock
- I've rewritten the Account Creation System to be a little more efficient, and in turn made it a little more complicated. I decided to do this due to the interest in the small project. It also now