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RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
16bit_ram
- 利用vhdl语言在fpga实现十六位的ram 使用非常方便-Using vhdl fpga implementation sixteen languages in the ram is very convenient to use
ramipcore
- 使用vhdl 语言在fpga环境下实现ram ip core-Environment in fpga vhdl language used to achieve ram ip core
16bit_ram
- 16位ram读写，基于vhdl，程序简洁易读，是非常好用的。-16 ram read and write, based on vhdl, program simple to read, it is very easy to use.
Add_Sub_4_Bit
- 这个是vhdl中很简单并且很基础的adder减法编码 主要是为以后的学习ram编码做准备 其中包括fulladder和halfadder-This is a very simple and very vhdl based adder coding is mainly for future learning ram preparation including fulladder coding and halfadder
fpgawritetoram
- fpga向RAM中写数据，数据宽度32位，利用VHDL编写。-FPGA write data to ram in 32bit data bus,write in VHDL.
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
ROM
- vhdl中的ROM程序，包括matlab表格程序，调用FPGA里的RAM实现ROM功能-The ROM vhdl procedures, including matlab spreadsheet program, call the FPGA to achieve ROM functions in the RAM
8051
- VHDL语言编写的SW8051IP核，并加入ROM,RAM,RAMX,PLL模块，可下载HEX文件并验证成功-VHDL language SW8051IP nuclear and add ROM, RAM, RAMX, PLL modules, you can download the HEX file and verify success
IDT7005
- 双端口静态RAM的VHDL程序，具体芯片型号为IDT7005-DUAL-PORT STATIC RAM
simple_ram
- the file about simple ram by VHDL code
CPU
- 简易CPU设计 利用VHDL编写。包含一个可以用于检验的LPM-RAM-DQ-CPU-design VHDL
635355963606373750
- 本文介绍了应用FPGA实现对高速A/D转换芯片的控制电路，介绍了这一控制的设计思想，并提出了通过双口RAM实现FPGA与慢速度的单片机进行双机数据通信处理的解决方案。- Data acquisition is an item of indispensable technology which is essential to the industrial control system. As the increasing need for speed performance of the da
rms_cal
- 基于VHDL的有效值求取，内含低通滤波子模块-RAM CAL with LPF by VDHL
single_port_ram
- Single port RAM file VHDL source code
small8
- This a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA. -This is a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA.
spram
- vhdl code of single port ram
PPRAM-test
- 乒乓缓存，用vhdl编写，用fpga内部ram-Ping-pong buffer, using vhdl to write,
dualporttst-1_1
- interfacing dual port ram in vhdl
2
- 用VHDL语言设计一个8位双向可控移位寄存器。 移位寄存器由D型触发器构成，采用串入并出形式。 采用VHDL方式设计一个16х4位RAM存储器-VHDL language to design an 8-bit bidirectional shift register controllable. The shift register by a D-type flip-flops, using the string into and out of form. Way design using