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reed-solomon
- Simulate, by using c++ ,a communication system consists of binary source, RS(7,3,5)/RS(128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS(7,3,5)/RS(128,122,7) BM decoder and sink。-Simulate, by using c, a communication system c
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
rs_decoder_spw
- Cadence SPW 4.8.2,RS解码的源码。-Cadence SPW 4.8.2, RS the source decoder.
FEC_EncodeAndDecode
- 实现RS-FEC擦除码的编码与解码，开发环境为VC2003。以解码为例，分析数据报文的API在FecDecInterface.cpp/h中，FEC解码的APIfec.cpp/h中。-RS-erasure code FEC coding and decoding, the development environment for the VC2003. A decoder for example, Analysis of data packets in the API FecDecInterface
OFDMtransmit
- 应用于无线通信的OFDM解调和RS解码源程序。64点FFT，19个子载波。调制 输入速率8K。-used in wireless communications OFDM demodulator and decoder source RS. 64-point FFT, 19 sub-carrier. Modulation rate of 8 K importation.
S3Demo
- Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simpl
rs255253
- Reed Solomon（255/253）纠错码的编解码器-RS is the short form for Reed-Solomon whih is a kind of algorithm for encoding. This package is the en-/decoder for the Reed-Solomon (255,253) error correction codes.
key_b
- 本程序主要通过外部中断INT0及3.3端口读取PS2键盘值并通过LCD1602显示，键扫描码的解码通过数组方式解码，程序的解码功能主要针对数字及大小写字母和常用标点符号 硬件描述：PS2键盘的时钟线（clk）接89S51的INT0（P3.2）,数据线data接（P3.3） LCD的控制端口分别为： RS = P2^7，RW = P2^6，EP = P2^5，数据端口为P0，液晶显示偏压VL必须接 -This procedure mainly through external int
verilogRS
- 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download th
LabVIEW
- 四选一数据选择器.vi 3-8译码器.vi 全减器.vi 时钟.vi RS触发器.vi-4 Select a data selector. Vi 3-8 decoder. Vi Full reduction device. Vi Clock. Vi RS flip-flop. Vi
S_81
- 内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等-There are 8-3 decoder, 8-bit adder, digital clock, digital display, 74ls138, 8,4 bit counter, d, rs flip-flops, adders, traffic lights, etc.
new_rs_erasures
- NEW Libraries in Encoder/decoder for RS codes in C
Rscodes
- Simulate, by using c, a communication system consists of binary source, RS (7,3,5)/RS (128,122,7) encoder, BPSK modulator, AWGN channel, coherent demodulator, RS (7,3,5 )/RS (128,122,7) BM decoder and sink.
rs_encoder_decoder
- RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
RS_dec
- rs（204,188）译码器，verilog实现，乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
psk_16_awgn_rs
- A Matlab-Simulink Model (.mdl) for implementing the psk(phase shift keying)-16 ary in AWGN Channel using RS (reed-solomon) en_Coder/decoder
RS(204-188)decoder
- rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。 仿真波形：
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
top_rs
- 利用Xilinx ise的IP CORE写的（255,223）编译码的程序(The use of Xilinx ISE IP CORE written (255223) encoding and decoding procedures)
rs_15_11
- ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)