搜索资源列表
Sdram_WR_FIFO
- 用SDRAM实现的写堆栈操作的verilog源代码-SDRAM write stack operations Verilog source code
sdram_mdl
- 基于verilog的SDRAM读写控制,源自特权同学-SDRAM controller use to read or write base on verilog，it is from teqian
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
SDRAM100M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是100M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 100m, the hope can help you
SDRAM_verilog
- SDR SDRAM用verilog语言实现-SDR SDRAM using verilog language
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
FPGA13_SDRAM
- 基于FPGA Verilog SDRAM 单字通讯-Based on the FPGA Verilog SDRAM words communication
sdram_latest.tar
- sdram 控制器 verilog 源码-verilog source of sdram control
sdram_verilog
- 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
sdram_module3
- 能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写-can complete read or write sdram， only include Verilog code and no simulation files
256M_sdram_OK
- 改自特权同学verilog语言写sdram测试程序；支持256M内存-verilog sdram
sdram_ov7670_rgb
- ov7670+sdram+vga显示的代码，用verilog写的 ，fpga开发时的参考资料-code ov7670+sdram+vga displayed with verilog written references when fpga development
MICRON_2048Mb_ddr2
- MICRON DDR2 SDRAM芯片Verilog仿真模型以及器件编号说明
SDRAM_96M_UART_TestOK
- SDRAM_96M_串口实验OK 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-SDRAM_96M_ serial experiments OK a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
DACtoADCtoSPI_Triangle1
- DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
SDRAM_CTRL
- SDRAM 读写的程序 用verilog 写的SDRAM的底层驱动-SDRAM literacy program
testsdram
- 一个用Verilog语言编写的SDRAM控制器源码, 逻辑清晰, 结构合理!-SDRAM controller is a source code in Verilog language, logical, reasonable structure!
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to