搜索资源列表
Bios
- S3C44BOX的BIOS。可使用的命令:help --- show help ? --- = help date --- show or set current date time --- show or set current time setweek --- set weekday clock --- show system running clock setmclk --- set system running clock setbaud ------ set
sdram_ctrl.tar
- SDRAM控制IP核的VHDL语言源代码,需要的开发环境是QUARTUS II 6.0。
H1wQqGvI
- 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL
sdramcontroller.rar
- 最完整的SDRAM控制IP核,包括源代码,仿真文件,以及IP核描述文件,包你用得上,SDRAM control of the most complete IP core, including source code, simulation, as well as IP core descr iption files, it can be helpful
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
Linux_bc
- 对vga接口做了详细的介绍,并且有一 ·三段式Verilog的IDE程序,但只有DMA ·电子密码锁,基于fpga实现,密码正 ·IIR、FIR、FFT各模块程序设计例程, ·基于逻辑工具的以太网开发,基于逻 ·自己写的一个测温元件(ds18b20)的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example(McGr ·这是CAN总线控制器的IP核,源码是由 ·FPGA设计的SDRAM控制器,有仿真代码 ·xili
socdesignandtest
- SoC是系统级集成,将构成一个系统的软/硬件集成在一个单一的IC芯片里,它一般包含片上总线、MPU核、SDRAM/DRAM、FLASH ROM、DSP、A/D、D/A、RTOS内核、网络协议栈、嵌入式实时应用程序等模块,同时,它也具有外部接口,如外部总线接口和I/O端口。通常,SoC中包含的一些模块是经过预先设计的系统宏单元部件(Macrocell)或核(Cores) ,或者例程(Routines),称为IP模块,这些模块都是可配置的,因此,基于SoC的设计方法学也称为基于IP的嵌入式系统设计
SDRAMTEST
- SDRAM控制程序,可以作为一个IP核使用, 比自带的功能要多 可以稳定运行-SDRAM control procedures can be used as an IP core, more than the built-in capabilities can be stabilized to run
netX
- 先进的 PLC 调试器 – 监视器 – 流程控制 – 单步运行, 断点 监视列表 采样跟踪, 示波器 – 在线读写, 强制, 在线变更 – 通过 TCP/IP 实现世界范围的远程连接-Another general issue of all DRAMs is the refresh. Fortunately, modern SDRAMs and SDRAM controllers know auto refresh modes. Depending on the
source
- SDRAM控制器源代码,是ALTERA公司的IP源核,很好很强大-SDRAM controller source code, very very strong
simulation
- SDRAM控制器,ALTEAR公司的IP原核的testbech,很难得-SDRAM controller, ALTEAR' s IP pronuclei testbech, hard to come by
quartus_IPcore
- 这15个Quartus的ip核里面有AVR,I2C,sdram,arm,usb,PCI等ipcoure,相信用过ipcore的人都知道这个的重要性,尤其是在NIOS嵌入硬件以提高速度的时候,这些事非常有用的。毕竟这些事人家封装起来的,肯定比自己去编好吧,献给用Quartus的好盆友,希望对你们有用。-free ipcoure
PCIeDDR2add
- PCIE-DDR2-双通道ADDA板主要用于AD数据的记录与回放。该板主要使用Xilinx公司的Virtex5 FPGA,通过PCIE IP核与主机通讯,存储系统包括DDR2 SDRAM和FLASH,为各种软件无线电技术的应用提供了一个非常强大的单插槽收发器解决方案。-PCIE-DDR2 dual-channel ADDA board is mainly used for the AD data recording and playback. The board Virtex5 the FPGA
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核,VHDL和VERILOG版本都有,希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
ddr_ddr2_sdram-ip
- 该程序为Altera 公司 DDR DDR2 SDRAM 的IP源程序安装包,非常有价值的东西,借此网址共享下。-The program for Altera Corporation DDR DDR2 SDRAM of IP source installation package, a very valuable thing, whereby the URL Sharing.
sdr_sdram
- sdram使用接口仿真,altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)