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uart
- 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
uart_verilog
- 用verilog语言编写的UART通信，经过调试可用。-edited in verilog language
UART_send
- uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
UART
- 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
UART
- 用verilog编写的UART串口通信程序，经验证误码率为0，系统由ARM控制FPGA的串口进行通信；-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
uart
- uart receiver, transceiver code in verilog
LIFO_Spartan3
- The code for a LIFO in verilog
UART
- 用Verilog实现的全局异步接收发送机，在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
c8_uart
- UART program in verilog
uart_hw_test
- uart hardware test in verilog
uart-master
- verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
uart
- FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)