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SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
uart_verilog
- uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
uart
- fpga 串行口 接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
fh_ram_s_w_r_16_512
- 单口串行可读写16x512的ram的verilog源代码-singal serial writeable and readable 16x512 ram
Proj
- verilog/vhdl 串行口232通信程序-Spartan3E开发板调试通过-verilog/vhdl serial port communication program-Spartan3E 232 development board debugging
RS232
- 基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)
uart
- 基于verilog的fpga串口通信,rx,tx.两根线(Basend on verilog fpga uart tong xin)
chuankou
- 此文件是一个串口verilog程序，一次传输一个字节，使用quartus编写(This is a program that is written in Verilog language ,It is a Serial program ,You can transfer and return a byte data.)
uart_test
- verilog写的串口发送机，虽然简单，但是注释写的比较清楚，适合新学习FPGA的同学作参考(Serial transmitter written in Verilog)
FPGA与SPI接口程序(hdl源代码)
- FPGA,VERILOG,SPI串口通信；(FPGA,VERILOG,SPI;;;;;;;;;)
project2
- 基于Verilog在quartus平台上搭建的串口通信模型，适用于初学者。本实验所用RXD的波特率为9600，TXD波特率为9600×16，1位起始位，8位数据位（ASCII码），1位停止位，无奇偶校检位。接收数据时，至少连续采样8个周期都是“0”后，才认定为起始位，之后每隔16个周期取一次数据。(Verilog based on the quartus platform to build a serial communication model, suitable for beginners.
ad706_test
- AD7606的FPGA驱动，AD7606与FPGA通过并行模式连接。FPGA可以将AD采集到的信号转换成电压信号通过串口输出，可通过PC机串口调试助手查看。实测可用(The drive program of AD7606 write by verilog. FPGA can convert the AD7606'sigal to volatage and send the converted signal to PC through uart.)
新建文本文档
- Verilog编写的按键代码，采用异步串口传输协议，并带有偶校验。(Verilog's key code, asynchronous serial port transmission protocol, and with even check.)
12345 keyuart
- verilog实现uart串口编程 FPGA板与PC传输数据(verilog uart processing FPGA and PC communication)
spi final
- verilog 实现spi 串口 通过FPGA板可以看出数据传输(verilog spi can be demonstrated with FPGA)
uart
- 基于verilog的串口通信 rs232串口 可以通过八路彩灯判断输入的程序
project2
- 基于FPGA实验板设计一个远程控制系统，接收由计算机发出的数据，和实验板上矩阵键盘输入的数据完成相应的运算之后，结果显示在实验板的数码管上，同时发送回计算机显示。(A remote control system is designed based on the experimental board of FPGA, which receives the data sent by the computer and completes the corresponding calculation wi