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DDS
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
signal
- verilog写的串口控制信号发生器,能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
dds
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
dds_var
- 自己写的一个简单的DDS控制器,此程序包包含完整的VERILOG写的程序,操作有点简单,输出正弦波,方波,锯齿波,通过键盘可以选择输出波形,与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through t
sin_50Hz
- 基于FPGA的50Hz的正弦波的产生,verilog语言-FPGA-based 50Hz sine wave generation, verilog language
sincount
- 用verilog语言开发的,ise产生正弦波的工程文件-Ise generate the triangular wave file
fankuizhendang
- 本程序是基于verilog HDL语言设计的反馈震荡电路的程序。其构成的电路叫振荡电路。能将直流电转换为具有一定频率交流电信号输出的电子电路或装置。种类很多,按振荡激励方式可分为自激振荡器、他激振荡器;按电路结构可分为阻容振荡器、电感电容振荡器、晶体振荡器、音叉振荡器等;按输出波形可分为正弦波、方波、锯齿波等振荡器。-This program is a feedback oscillator circuit design based on Verilog HDL language program
da--sine
- 利用dds方法,通过DA输出正弦波,频率1KHz 频率根据代码可调-DA output sine wave frequency 1KHz (Verilog)
verilog_sine-wave-generator
- verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
sine_wave_2011_0329
- 正弦波波形发生器,verilog编写,Modsim仿真。-sine wave genonter
xinhao
- 基于verilog的数字信号产生器,包括三角波、方波、正弦波,频率可调。-Verilog-based digital signal generator, including a triangle wave, square wave, sine wave, frequency adjustable.
DDS-SIN
- 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
sinw
- 用verilog写的正弦波发生器,QuartusⅡ环境-Sine wave generator written in Verilog
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
verilog_dds
- verilog实现dds,用于FPGA产生正弦波,适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
dds_project
- DDS直接数字频率合成器,能产生正弦波,方波,锯齿波,三角波四种波形,同时能在12864上显示波形类型和频率,用FPGA verilog实现的-DDS direct digital frequency synthesizer can produce sine, square wave, sawtooth wave, triangle wave four waveform, while in the 12864 on display the waveform type and frequency
frequency
- 能够检测方波正弦波以及锯齿波的频率,并且以及试过可以运行,采用的开发环境是ISE,编程语言是Verilog-Able to detect a square wave frequency of the sine wave and sawtooth wave, and as well tried can run the development environment is the ISE, the programming language is Verilog
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
dds_mul
- 简单的多周期dds的verilog编程,出来一个正弦波,可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波,13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask