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zhengxiansanjiao
- 用Verilog实现正弦波和三角波,验证过的,功能正确-Sine wave and triangular wave with Verilog and verified correct function
e
- 基于verilog语言编写的代码。功能:可实现三角波,正弦波,方波的测量。-Based on Verilog language code. : Triangle wave, sine wave, square wave measurement.
zhengxianbo
- 正弦波发生器,基于verilog语言编写的,不用用DAC模块,直接输出0和1电频,经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
FIFO
- 将ROM的正弦波数据输入FIFO存储器,然后输出,有modelsim仿真波形-Verilog FIFO ROM mif sine
sinwave
- 使用verilog hdl语言编程正弦波信号,能仿真出结果-Can use verilog HDL language programming sine wave signal, the simulation results
dds_compiler_v4_0
- Verilog的DDS实现正弦波输出。这个模块是不可综合的,但是已经综合了,-Verilog DDS
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序,发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
SIN_GNT
- LPM_ROM定制。简单的正弦波发生器。 Verilog HDL语言设计。 EP4CE15F17C18N实测可用。-LPM_ROM customization. Simple sine wave generator. Verilog HDL designs. EP4CE15F17C18N measurement available.
DDS2
- 基于Verilog语言的正弦波的产生,应用了基于直接数字频率合成器的方法。-Verilog language generated based on the sine wave, the frequency of application of the direct digital synthesizer based methods.
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
wave_gen
- 波形发生器,可以产生正弦波,锯齿波,方波。Verilog语言编写-Waveform generator, can generate sine wave, sawtooth wave, square wave. Verilog language
SinGen
- 使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件-Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
sinewave-case
- 利用verilog语言以及case语句实现正弦波波形,并利用modelsim完成波形仿真。-Use verilog language and case statement to achieve sinusoidal waveform, and use modelsim complete waveform simulation.
sin_quartus9.0
- 用Verilog实现不同相位的正弦波波形输出,使用到ROM查表方式,对不同相位的地址进行合成后查表得到不同相位的正弦波。-Implementation of Sine wave output with different phase.
sine
- FPGA实现正弦波信号的产生,verilog语言-FPGA realization generate sine wave signal, verilog language
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序(已验证)Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
dds_generater
- 波形发生器,可以生成正弦波、三角波、方波、锯齿波;可以选择输出频率和幅度,基于DDS设计,verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM,通过调用内部数据实现正弦波输出,开发环境quartusii , 语言verilog , 调试通过 , 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
codic
- codic算法代码,verilog,可产生正弦波,求正弦,余弦值。(useful codic, verilog HDL and test benth program)