搜索资源列表
IFFT
- ifft 的verilog程序，最好在ISE9.2的平台上实验-ifft the verilog program, the best experimental platform in ISE9.2
PRIORITY_ENCODER
- A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input
XHDL3.2.52
- this is a verilog to VHDL tool.
DE2_TV
- 基于DE-2板的TV--box开发，verilog程序的开发-Based on DE-2 board TV- box development, verilog program development
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
Example-8-2
- Verilog延时建模设计 Example-8-2目录下为设计工程子目录，目录中包含以下内容。 1. Blocking_LHS_Delay：阻塞赋值左式延时。 2. Blocking_RHS_Delay：阻塞赋值右式延时。 3. NonBlocking_LHS_Delay：非阻塞赋值左式延时。 4. NonBlocking_RHS_Delay：非阻塞赋值右式延时。 -Delay Modeling Verilog Design Example-8-2 design engi
i2c-(2)
- de2 board using fpga plat form verilog code for i2c concept
Introduction-to-Verilog
- Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n
verilog-programs
- These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These progra
Verilog
- 第1章 Verilog HDL入门2008 第2章 Verilog的模块2008 第3章 Verilog的基础知识2008 第4章 Verilog的语句2009-Chapter 1 Introduction to Verilog HDL Verilog 2008, Chapter 2, Chapter 3 of the module in 2008 the basics of Verilog 2008, Verilog statements in Chapter 4, 2009
BPSK
- 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
LCD-16-x-2
- It is verilog code of lcd 16 x 2.
Basic-Knowledge-of-Verilog-HDL
- 该讲稿从两个方面介绍了verilog HDL的基本知识： 1.verilog HDL的基础语言知识, 2.verilog-XL仿真 -Basic Knowledge of Verilog HDL
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
booth
- radix 2 booth multiplier verilog code
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
OV7670initial
- ov7670硬件初始化代码，运行在alteral cyclone 2 fpga上-the hardware initializition of ov7670,running at cyclone 2 fpga platform
verilog
- 里面总共有三个程序，功能是实现2\3双模分频的功能，同时比较了阻塞与非阻塞语句的区别；-It has a total of three programs, the function is to realize 2, 3 dual mode points the function of the frequency, and compared with the obstruction of obstruction statement difference
VerilogHDL-Code-Formatter-V1.2
- 这是一款Verilog代码格式化工具. 用于代码格式美化。您可以根据自己的VerilogHDL格式需求，在右侧控制面板中进行控制，左侧即时显示出当前设置的格式。是一款好用的VerilogHDL代码格式工具。-Format landscaping. According to their own VerilogHDL format requirements, you can in the right side of the control panel to control the real-time
verilog-code-for-varying-pulses
- The program is written in verilog. The code is written to output a sequence of pulses with a width of that of the clock. the sequence is in the order of 1,2,3,1,5 ms delay