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risc8
- 一个功能简单的八位cpu，适合刚入门的FPGA Verilog 编程，试过能用！-A simple function of the eight cpu, just portal for FPGA Verilog programming, tried to use!
avr8_latest.tar
- AVR8 cpu的verilog 源码 欢迎下载使用 AVR8 cpu的verilog 源码 欢迎下载使用-AVR8 cpu s verilog welcome to download source code verilog using AVR8 cpu s welcome to download AVR8 cpu welcome to download the source code verilog
sub86_latest.tar
- x86 cpu的verilog 源码，欢迎下载使用。 x86 cpu的verilog 源码，欢迎下载使用。-x86 cpu s verilog source code, welcome to download. x86 cpu s verilog source code, welcome to download. x86 cpu s verilog source code, welcome to download.
avr_core_latest.tar
- avr cpu verilog 源码实现，欢迎下载使用-avr cpu verilog source implementations are welcome to download
lab07
- 利用verilog语言编写一个单周期cpu实现加减乘除等十六条基本指令，模拟仿真通过。-Use verilog language to achieve a single cycle of addition, subtraction, etc. cpu sixteen basic instructions, simulation pass.
proc_pipe
- A 5 stage pipeline CPU written in verilog codes
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
LC3_CPU
- lc3 cpu 的verilog实现 lc 3 cpu 的verilog实现-lc3 cpulc3 cpu lc3 cpulc3 cpu lc3 cpulc3 cpu
pro_2
- 简单CPU设计。使用Verilog语言，比较简单易懂。-simple CPU
singleCPU
- 用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.
muCPU_final
- 用Verilog开发的多周期CPU,可执行mips汇编中的R\I\J型指令，具有较高的参考价值。-Using Verilog development of multi-cycle CPU, mips executable compilation of R \ I \ J-type instruction, with a high reference value.
all_cpu
- 精简指令集CPU，可完成移位，跳转等简单功能，适用于FPGA学习，本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
CPU_MODEL
- implementation of CPU model using verilog
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
SensorHubDesignFilesSourceCode
- sensor-hub技术是最新出来的技术，目前用在智能手机领域，手机里面的传感器越来越多，这给CPU带来很大的负担，功耗也随之提高。sensor-hub技术出来后，可以有效的解决这个问题，这是运行在lattice FPGA平台上的verilog源代码，欢迎大家一起交流学习，希望能给你带来帮助。-Sensor- the hub is the latest technology, the current use in the field of smart phones, mobile phone i
mpi
- MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。本资料包含verilog程序以及说明-MPI interface is an interface for communication between the CPU and logic, the general way of using the bus, the bus there are two standards, one is the MOTO mode, th
OpenMIPS_VerilogHDL_Study_v1.1
- 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
LC3_CPU-varellow
- LC3 CPU的仿真，使用Verilog语言编写-Simulation LC3 CPU using Verilog language
pipeline_mipscpu
- 运用Verilog语言实现MIPS五级CPU的功能，能下载实现-5-level MIPS CPU based on Verilog