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acc32bit 本设计为32位数字相位累加器
- 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level descr iption of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
cla4
- verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位-verilog code4-bit carry look-ahead adderoutput [3:0] s// summationoutput cout// c
bitadder
- 一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习-A full adder, VERILOG implementation, including test papers, test available, please download, a common study
16weijiafaqi
- 本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.-This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe.
Common_adder_verilog_design
- 上传文件为：常用加法器verilog设计.rar-Upload files as follows: common adder verilog design. Rar
select_adder
- implement of select adder with verilog
Adder_Verilog
- 对于Verilog初学者非常实用的代码，帮助了解许多常用的加法器-Very useful for beginners Verilog code to help understand the many commonly used adder
add_sub
- basu verilog codes for adder subtracor etc
FullAdderDesign
- Verilog Code For Full Adder
bitadder
- verilog code for 4 bit adder
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
add_16bits
- 這是16bits加法器,利用verilog程式撰寫-adder-19bts
full_adder_code_in_verilog
- full adder in verilog
fadd
- it is verilog code for floating point adder
ex1.v
- 用Verilog HDL 实现的4位二进制全加器。-4-bit full adder implemented with Verilog HDL
chengxu
- 加法器 比较器verilog hdl 等简单小程序 新手学习中 见谅-Adder comparator verilog hdl Adder comparator verilog hdl a small way as simple novice learning apologize
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C