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fallthrough_small_fifo_v2
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short
93317478verilog.HDL.examples
- FIFO,加法器，乘法器的VERILOG语言-fifo
asy_FIFO
- 用Verilog实现FIFO的异步设计，里面有详细的代码和各个模块的代码，经过调试可以使用-asynchronous FIFO design
fifo_syn
- 本源码是用VERILOG实现FIFO的读取，并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
sdfsdFifo
- 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
LZY
- 基于FPGA的软FIFO代码实现，双时钟，异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
USB_SLAVE_700AN_RD
- 基于verilog 代码的USB2.0同步FIFO读代码-USB2.0 syn FIFO read
sync_fifo
- 一种同步的先入先出verilog程序，可正确地通过编译-a programe of fifo wrote by verilog
IPcore_fifo_testbench
- 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
UART_FIFO
- Verilog 语言描述，基于FIFO设计的UART。Quartus 10中编译通过-Verilog language descr iption, based on the design of the UART FIFO
foio
- verilog语言写的先进先出（FIFO）电路-verilog language written in FIFO (FIFO) circuit
SPI
- 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
uartfifo
- 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
my_FIFO
- FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
rx_fifo
- verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
fifo_4X16
- 完整的FIFO Verilog程序，经过仿真验证，直接可用-FIFO Verilog
fifo_verilog
- FIFO的verilog实现,内含PDF说明和已建好工程。-Implementation of FIFO using verilog