搜索资源列表
uart
- 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
uart_1203_4
- MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o
System_Demons
- 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实
FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
afifo
- verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
fifo_uart
- 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
NANDFlashcontrolandFIFOcontrol
- 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
Example1
- fifo verilog hdl along with test bench its hardware
Syn_FIFO
- 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
uartfifo
- verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
versatile_fifo_latest.tar
- Verilog HDL语言编写的通用FIFO，让你更加了解FIFO的原理-versatile fifo based on verilog hdl.
async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
uartfifo
- 利用verilog开发的串口FIFO程序，比较基本，包含完整的工程-The verilog developed serial FIFO procedures, more basic, including the complete project
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
024-DAC902
- verilog控制dac902的程序，先从fifo读取数据-the verilog control the dac902 procedures start fifo read data
022-FIFO_PRO
- verilog写的控制quartus自带fifo ip核的程序-verilog to write the control quartus own fifo ip nuclear program
aFIFO
- 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
sram_fifo_uart
- 用verilog HDL编写的SRAM+FIFO+UART模块，欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module