搜索资源列表
fifo_ctrl
- fifoctr 寄存器控制 verilog代码-FIFO ctr
aasyn_fiffos
- verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
fifo_module
- verilog 语言写的FIFO历程，可以很好参考。 -The write FIFO verilog language course, a good reference.
LL
- verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
fifo_uart
- uart的verilog代码,包含fifo，并且采用过采样以防止噪声的干扰-uart verilog code
generic_fifos_latest.tar
- fifo的verilog代码，包含rtl，sim，testbench内容的verilog代码，完全可用-rtl code of a fifo
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
FIFO_V1
- 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
fifo_rd64
- 实现64位数据位宽的fifo的功能,用的是verilog代码。-Fifo functionality
uart_fifo_design
- verilog语言时序的异步读写FIFO，请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
asyn_fifo_bk
- 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
prj_5
- FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
61EDA_C2212
- 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
UART_FIFO
- Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and