搜索资源列表
coeff_rom_1_6
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
coeff_rom_3_4
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
beta
- Fir verilog code implemented to find out the output of fir filter
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
fir
- 使用verilog语言实现的fir滤波器，使用了内部的触发器资源，优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
verilogFIR
- 基于verilog的FIR滤波器程序设计（调试过的）-verilog
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Xilinx-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
fir_filter_verilog
- FIR filter verilog project
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
FIR64tap
- 使用verilog语言实现64阶FIR,调试可以通过-64 taps FIR with verilog
fir
- 做作业的时候用VERILOG编写的FIR滤波器程序，希望对大家有用-Homework time FIR filter with VERILOG written procedures, we want to be useful
FIR
- FIR filter using verilog code
FIR
- 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
VerilogFIR
- low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
fir_lms
- finite impulse response LMS algorithm verilog code
verilog-fir
- 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
fir
- 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)