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该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行-This file is booth multiplier verilog code, after the final simulation, can be directly run
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fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
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pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language
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fpga implementation of fast radix 10 multiplier using verilog code
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一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
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multiplier code using verilog
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verilog code for shifting of multiplier
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its a verilog coding of a multiplier.
it multiply 2 values each of width having 4bit
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this code is used for designing multiplier by using verilog code
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FPGA用verilog实现串口和电脑的字符串以及单字符精准无误通信，即通过电脑向FPGA发送任一长度数据，FPGA返回PC相同的数据。波特率为9600，本例程为了得到精准的波特率使用了50M时钟的3倍频，测试可用，如有不明的地方，可以给我留言-FPGA implementation using verilog string and the computer serial port and single-character accurate communication, 9600, FPGA u
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A classic booth multiplier implemented using verilog HDL using the Xilinx software.
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128位乘法器，verilog实现，椭圆加密算法-128 multiplier, verilog achieve, elliptical encryption algorithm
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采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
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用verilog代码来实现并行序列乘法器，采用乘法器结构，读者可以自行编译，-Use verilog code to implement a parallel sequence multiplier, using the multiplier structure, readers can compile their own,
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verilog code for floating point multiplier
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Booth algorithm multiplier
this project design booth multiplier by verilog language. you can open it by ISE and simulate.
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verilog function实现全组合逻辑乘法器电路，位宽可配置，高效-Function purely combined logic circuit to achieve the function of the multiplier, configurable bit width, high efficiency.
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Wallace nultiplier design using 3-2 compressor based on universal gates. verilog HDL is used to design this multiplier
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DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
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经过改良的乘法器，硬件实现，FPGA，verilog源码-Improved multiplier, hardware implementation, FPGA, Verilog source code
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