搜索资源列表
muil
- 基于verilog的乘法器 简单实用 初学者的好材料-Verilog multiplier based on simple and practical good material for beginners
multiplier
- paralel multiplier in verilog
Booth_Multiplier_8bit_Radix_4_With_12bit_Adder_Ko
- verilog code for Booth Multiplier 8-bit Radix 4
Multiplier
- verilog implementation of the 32bit multiplier
multiplier
- this source code is one example to build multipler in verilog HDL.
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
multiplierunit
- VHDL/FPGA/Verilog 实现乘法器的功能-use VHDL/FPGA/Verilog multiplier unit
Small-multiplier
- 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
IIR_filter
- 本实例利用硬件乘法器实现一个IIR滤波器。文件包含实现的verilog代码。-The example used to implement a hardware multiplier IIR filter. File contains the implementation of the verilog code.
multiplier
- 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
booth
- radix 2 booth multiplier verilog code
pipe_mul8
- verilog实现的流水线8位乘法器，效率高，代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
multiplier
- 参数可配置的sequential 乘法器和booth 乘法器-verilog source code with configurable parameters for sequential multiplier and booth multiplier
Floating-Point-Multiplier-in-Verilog
- Floating Point Multiplier in Verilog
16-parallel-multiplier
- 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
multiplier
- 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
Multiplier
- 圖形介面乘法器,也可自行使用verilog去改-Graphical interface multiplier, also free to use verilog go and change
MULT
- 用VERILOG实现乘法器功能，通过仿真验证-With VERILOG multiplier function is verified by simulation