搜索资源列表
usbhostslave
- USB主机和设备的verilog代码，实现了USB1.1协议规范的要求-USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements
usb_funct
- usb1.0的核，有详细的usb核的设计源码，用verilog语言编写，同时附有相关的设计文档，质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
usb_ctr
- usb的verilog 代码。对理解usb的原理有很大帮助，并可以在nc环境下仿真。-usb the Verilog code. Usb to understand the principle is very helpful, and to be nc simulation environment.
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
usb_host-usb-fpga
- 基于FPGA的Verilog语言设计的USB程序，适合初学者-Verilog language based on the FPGA design of USB application, suitable for beginners
usb
- Altera usb example verilog file.
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
USB
- 实现FPGA与PC通信的USB2.0接口,采用verilog语言实现-Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve
USB
- verilog 实现USB传输功能，包括A/D转换、驱动程序等-vrilog usb
usb11_sim_model_latest.tar
- VHDL/Verilog implementation
usb_veriloghdl
- USB是 FPGA设计，verilog语言实现(USB is FPGA design, Verilog language implementation)
13_usb_test
- fpga usb2.0 cy7c68013 黑金的板子(fpga usb2.0 cy7c68013)
ezusb_io_latest.tar
- CY7C68013实现FPGA控制的USB接口通信，已通过测试(CY7C68013 FPGA control to achieve the USB interface communication, has passed the test)
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
usb_rd_buffer
- FPGA（SPARTAN6）通过USB协议与开发板上的USB芯片进行数据读写测试，在上位机上可以看到USB发来的数据，也可以通过修改VERILOG代码完成数据的接收(FPGA (SPARTAN6) can read and write data through the USB chip on the development board through the USB protocol. The data sent by USB can be seen on the host computer,
CAN总线，I2C，USB等的FPGA实现源码
- 控制器局域网总线协议的Verilog代码(The Verilog code of the CAN bus protocol)
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发，包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)
kwmltable-operand
- RS码的FPGA实现,verilog语言形式,好参考资料()