搜索资源列表
Snake
- Verilog, Snake game, VGA, Keyboard
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
vga_timing_gen
- verilog文件 实现VGA时序驱动，产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
lab8_wena_Arturo
- vga verilog code for showing the vga pattern and diferent functions for a Spartan develp card
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
yavga
- This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable chars
DE2_NIOS_HOST_MOUSE_VGA
- 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
TrackingPresentation_jon
- presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board wi
61EDA
- 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌 入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案， 针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a varie
vga
- vga显示程序，用verilog 语言编写，程序运行测试完全没有问题。-vga display program, with verilog language, the program run the test is no problem.
S6_VGA
- 利用cpld作为控制器实现驱动vga显示器，虽然只有8位色，但是实现方式只得借鉴-cpld verilog vga
vgactl9
- EPM240+IS61LV1024+VERILOG实现简单的VGA控制器,RGB各1bit,与AT91SAM7S64接口.-EPM240+ IS61LV1024+ VERILOG to achieve a simple VGA controller, RGB each 1bit, and AT91SAM7S64 interface.
MTDB_VGA_TV
- Verilog语言，NTSC格式，pal格式（稍作修改）的模拟信号转换成数字信号，在VGA显示器上显示-Verilog ,pal , NTSC , VGA
vgav2
- fpga vga 输出，60HZ 640*480 8位灰度图像 采用verilog语言编写-fpga 640*480 60HZ vga output，writed in verilog
altera_up_avalon_vga
- VGA altera官方例程Verilog代码 详细说明很好很实用-VGA altera detailed descr iption of the official routine Verilog code for a very good very practical
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input
VGAverilog
- 这是用于VGA显示源代码verilog，希望对大家有用-verilog VGA
vga
- vga_control for verilog
vga
- 小学期内容 硬件描述语言verilog 控制VGA显示-Primary verilog hardware descr iption language of content control VGA display