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verilog50%
- 本文主要介绍了50%占空比三分频器的三种设计方法,并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD,在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the
jicifenpinqi
- 别人编写的奇次分频器,用VHDL写的,我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
jhvhjhk
- 乒乓球游戏机实验报告实验人: 大火虎设计课题: 用VHDL设计一个乒乓球游戏机,用开关来摸拟球手及裁判,用LED来模拟乒乓球,采用每局十一球赛制,比分由七段显示器显示. 设计思路: 采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分,显示,键盘控制。设计过程: 1) 对4MHZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD(注:仿真时所加的信号频率比这要高。)。 2) 设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,
my_design_frequency
- 在数字电路中,常需要对较高频率的时钟进行分频操作,得到较低频率的时钟信号。我们知道,在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述,在源代码中完成对时钟信号 CLK 的 2 分频, 4 分频, 8 分频, 16 分频。 这也是最简单的分频电路,只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
Digital_system_design_example
- 数字系统设计实例.pdf,VHDL语言实现,7.1 半整数分频器的设计7.2 音乐发生器7.3 2FSK/2PSK信号产生器7.4 实用多功能电子表7.5 交通灯控制器 7.6 数字频率计.值得一看。-digital system design examples. Pdf, VHDL, 7.1-integer divider design Music Generator 7.2 7.3 2FSK/2PSK Signal Generator 7.4 Practical multi-functi
ndivider
- VHDL源代码实现任意个分频,值得推荐学习-VHDL source code to achieve arbitrary sub-frequency, it is worth learning recommended
VHDL_FOR_DIV
- 清楚地讲述了怎样用VHDL语言设计整数分频、小数分频、分数分频等,是学习VHDL不可多得的好材料!-clearly described how to use VHDL design frequency integer, decimal fraction frequency, the frequency scores. VHDL is learning very good material!
N_counter_VHDL
- 任意N进制分频器的标准VHDL代码(原创)-arbitrary N divider 229 standard VHDL code (original)
even_divider_VHDL
- 常用2、4、6及任意偶数分频器的VHDL代码实现(原创)-used 2,4,6 and even arbitrary divider VHDL code to achieve (original)
odd_divider_VHDL
- 常用1、3、5及任意奇数分频器的VHDL代码实现(原创)-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT,带源码,解释详细,一步一步学习,是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
070330
- VHDL三分频程序 VHDL三分频程序-VHDL third frequency procedures VHDL third frequency procedures VHDL third frequency procedures
52_divider
- 分频器,用VHDL语言编码,可能对你用处不是很大,但做为参考还是很大用处的-dividers, VHDL coding, you may not have much use, but as a reference or very useful
Odd_Fren
- 一个3分频的VHDL程序,方便学习且仅供学习之用-a frequency of three minutes VHDL procedures, facilitate learning and learning purposes only
clk_div
- 自己编写的任意分频VHDL程序,程序简单,以供大家分享!-prepare their arbitrary frequency VHDL procedure is simple and for all to share!
VHDLnf
- VHDL实现任意整数分频,--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
eb894854-c49f-4ba1-a258-411bc31cf6eb
- 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计,并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分,整个自动控制系统由四个模块构成:秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能,其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠,应用于实际当中有较好的实用价值和较高的可行性
fenpinqi
- 《分频器设计》绝对好用的EDA实验程序!已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
LED_clock_quartus
- 用VHDL语言实现数显时钟,devid200.vhd为分频模块,scan.vhd为LED扫描模块,timecount.vhd为计数模块-VHDL digital clock, devid200.vhd for frequency module, scan.vhd for LED scanning module, timecount.vhd for counting module
fenpinqi11
- 基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)-divider based on FPGA design, has adopted the simulation (VHDL language)