搜索资源列表
FPGAzigzag
- 三角波发生器，VHDL语言描述，通过信号分频等实现波形发生，已经在示波器上验证了，效果不过。-Triangular wave generator, VHDL language descr iption, such as through the realization of the signal waveform frequency has been verified on an oscilloscope, the effect, however.
fenpin
- 此程序是用硬件描述语言VHDL编写的分频程序，实现了不同的频率输入。-This procedure is the preparation of hardware descr iption language VHDL sub-frequency procedures, to achieve a different frequency input.
clk_8
- 一个八分频的VHDL程序,经过编译和仿真.-An octant of the VHDL-frequency procedures, after the compiler and simulation.
clk_3d
- 一个1.5分频的VHDL程序,经过编译和仿真.-A frequency of 1.5 points VHDL program, after compiling and simulation.
div5
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器）-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler)
electronicorgan
- 电子琴VHDL程序包含有：顶层程序、音阶发生器程序、数控分频模块程序和自动演奏模块程序-VHDL flower contains are: top-level procedures, scale generator procedures, numerical control frequency module procedures and module procedures performed automatically
phase_lock_vhdl
- 在VHDL下实现锁相环的源码和说明文档.通常用于分频或倍频时进行相位锁定.-To achieve phase-locked loop in the VHDL source code and documentation. Normally used when the frequency or frequency-doubling phase locked.
ch5_8
- 用VHDL写的一个5/8分频器,希望对刚学习VHDL的朋友有帮助-Use VHDL to write a 5/8 prescaler, and they hope to study VHDL friends just have to help
dividefrequency
- 如何用VHDL语言对时钟进行分频以达到计数目的-how to achive counting by VHDL Language
cpld
- 工程中使用的一段资源管理vhdl程序,有简单的分频代码等，希望能给你帮助-a vhdl program use in my prj ,may be give u some help
fpq
- ISP实验分频器源程序，用VHDL写的，在x3s200an芯片上编译的-ISP prescaler source experiment, using VHDL written in compiled x3s200an chip
clk_div.vhd
- 实现对时钟信号的技术分频，程序简单易懂，对于初学VHDL者来说，提供了一个良好的方法。-Implementation of the clock signal frequency technology, the program easy to understand, for the beginner who VHDL, provides a good approach.
ClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
0zzClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
hehaClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
clk_div
- VHDL描述的时钟分频电路，用途广-VHDL descr iption of the clock divider circuit, uses widely ...
single_clock_divider.tar
- 关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助-DIVIDE
shukongfenpin
- 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of desig
yinyuefenpin
- 十二音阶和八度分频的硬件描述语言VHDL程序，测试通过成功-12 sub-octave scale and frequency of the hardware descr iption language VHDL procedures, test the success of