搜索资源列表
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
encog-core-1.1.0
- VHDL制作的ann的code，希望大家可以用来作为参考-VHDL produced ann of the code, hope that can be used as a reference
ch8ex
- 几个简单数字逻辑电路的VHDL代码，带有简单的说明-A few simple digital logic circuits VHDL code, with a simple note
pn_gen_vhd_211
- 通信中常用的PN序列产生器的源代码全部打包-Communications commonly used in PN sequence generator, the source code of all packaged
Baseband_line_code
- 本课程设计完成了基带线路码产生电路的设计，数字基带信号的传输是数字通信系统的重要组成部分之一。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。为使基带信号能适合在基带信道中传输，通常要经过基带信号变换，这种变换过程事实上就是编码过程。本些课题实现了这样的编码过程。-This course is designed to use VHDL hardware descr iption language completed the base-band circuits hav
ARM7_HDL
- ARM7 verilog vhdl code
matlab_to_vhdlfpga
- 本文提出了加快发展之路 从理论设计,通过Matlab / Simulink环境 在定点算法对其行为模拟的 在FPGA或定制实现硅片。这个了 实现了netlist移植的Simulink系统 描述成的硬件描述语言[VHDL]。在这个例子中,这个 Simulink-to-VHDL转换器被设计来使用 代码来描述结构VHDL系统互连, 允许简单的行为说明基本模块。 结果VHDL bit-true交付后代码 比较定点Simu
machester_VHDL
- manchester码在通信领域中用途广泛 这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦-manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare
fifo
- fifo example vhdl code
75448172geleicounter
- 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
program-example-code
- mini2440非操作系統下的測試源碼,包括對板上所有硬體,介面,記憶體...的測試源碼.例cmos攝像頭等,都包含在內.-mini2440 test under non-operating system source code, including all on-board hardware, interface, memory test source .... Example cmos camera in first class, are included.
Fundamentals.of.Digital.Logic.with.VHDL-source.ZIP
- <数字逻辑与VHDL设计>代码 作者：STEPHEN BROWN，ZVONKO VRANESIC 边计年译 -《Fundamentals of Digital Logic with VHDL》 [Brown,Vranesic-2005] code Bian Jinian Translation
frequency_measured_amplitude_phase_measurement
- 2008年北京市大学生电子设计竞赛程序源代码[测频率，测幅值，测相位]。进过竞赛测试性能良好，获奖作品-Beijing 2008 Undergraduate Electronic Design Contest source code [test frequency, measured amplitude, phase measurement]. Progressive had a good race to test the performance, winning entries
ElectronicCodeLock
- 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
gold_code_vhd_217
- Gold Code Generators in Virtex Devices
testbench
- ddr sdram controller datd module source code
VHDLcodeofMPSK
- 基于VHDL硬件描述语言，对基带信号进行MPSK调制（这里M=4）-VHDL code for MPSK
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.