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coeff_rom_2_5
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
rmfilter
- 低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
ldpcverilog
- verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
svc_timer33ms
- Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co
FSK_modulation_and_demodulation
- 模拟数字通信通道，将离散数据利用奇偶效验码编码，FSK调制后，发送，接收端解调解码后还原-Analog-to-digital communication channel, the use of discrete data to be well-tested code parity coding, FSK modulation, the transmission, the receiving end to restore the decoded demodulation
avr_core2
- avr core porocesssor vhdl source code
rs_encode
- 这是用verilog编写的RS（204，188）代码，适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
55593379usb(FPGA)
- this a vhdl code for a bus-this is a vhdl code for a bus
USB_code
- this a vhdl code for usb-this is a vhdl code for usb
ebook_USB2.0_intel_tranceiver
- High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor
dlx
- DLX CPU VHDL CODE UNIVERSITY
PSK
- 关于PSK调制与解调的VHDL程序及仿真-PSK modulation and demodulation on the VHDL procedures and simulation
eth_interface
- 基于FPGA的以太网接口的实现。 使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可。-FPGA-based Ethernet interface. Use: 1. Copy to your hard disk. 2. With ISE to create items to the various code files, you can.
HammingDecoder
- -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee U
rom
- 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit)
filter_final
- compiled vhdl code for fir filter
cordic
- COriac Algorithm code
SEG7_LUT_8_0
- DE2开发平台7段显示VHDL代码，自己针对vilorg翻译成VHDL代码-DE2 Development Platform 7 show the VHDL code for vilorg translated into their own VHDL code
crcsend
- 用vhdl代码实现循环冗余检验，CRC即Cycic Redundancy Check-Vhdl code used to achieve the cycle redundancy check, CRC that Cycic Redundancy Check