搜索资源列表
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
dds2
- 同样逻辑分析仪中部分硬件描述语言VHDL做的DDS模块，-The same part of the logic analyzer in VHDL hardware descr iption language modules do DDS,
dds_first
- 用vhdl语言，通过加法器和寄存器实现fpga的dds功能-Using vhdl language, and register through the adder to achieve the fpga functional dds
ddsm
- 用vhdl实现dds功能的程序试一试看看是不适合你！-Dds feature using vhdl program to try to achieve a look is not for you!
!DDS_vhdl
- 采用DDS（直接数字频率合成）方法，用VHDL编写，源程序-Using DDS (direct digital frequency synthesis) method, using VHDL written source
DFF_BDF
- 利用VHDl语言实现的DDS正弦信号的输出-dds
acum_hdl
- phase accumolator in vhdl & test bench for it for dds-phase accumolator in vhdl & test bench for it for dds
DDSreport
- 使用VHDL语言完成DDS的详细设计，可以作为课程设计使用-Using the VHDL language to complete the detailed design of DDS can be used as a curriculum design
ddsgt
- 采用DDS技术，在Altera 8.1软件下，利用VHDL语言编程，从而产生正弦波信号，经调试，文件正确可用-Using DDS technology, Altera 8.1 software, using the VHDL language programming, resulting in sine wave signal, after debugging, documentation is available right
MD_DDS_10bit_VHDL
- 十位DA输出的DDS，用VHDL实现，环境：ISE 8.1，仿真软件：ModelSim_SE_6.1b-10 DA output of the DDS, with the VHDL implementation, environment: ISE 8.1, simulation software: ModelSim_SE_6.1b
renyiboxing
- 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究 的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储 于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町 以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of wav
sin5
- DDS FPGA 正弦波 VHDL语言-DDS FPGA 正弦波 VHDL语言
sin7
- DDS FPGA 正弦波 VHDL语言-DDS FPGA 正弦波 VHDL语言
dds_vhdl
- 直接数字综合器DDS的设计（VHDL语言）-design of DDS(language of VHDL)
dds_vhdl
- 该源码为VHDL语言编写DDS生产正弦波信号源码-The DDS source for the VHDL language production of sine wave signal source
DDS_100325(13)_success
- QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi
dds_dds
- DDS信号发生器，用VHDL写的，编译用qartus通过，测试是好的，好东西大家一起分享啊，希望能对大家有帮助啊-DDS_DDS
DDS_TEST
- 此文件为DDS的测试文件,用VHDL语言编写。可供参考。-DDS test
ISE_lab18
- 基于VHDL语言，通过调用Xlinx生产的FPGA开发板上的DDS核，产生正弦信号。并可进行仿真观察。-Based on VHDL language, by calling Xlinx FPGA development board produced by the nuclear DDS, sine signal. The simulation can be observed.
FREQENCYrar
- 这是用DDS原理实现的频率计，能够测量1到999999HZ的待测信号，包括VHDL源程序以及成型的BDF文件。-This is achieved with a frequency meter DDS principle, can measure a signal under test to 999999HZ, including VHDL source code, as well as forming the BDF file.