搜索资源列表
example10
- VHDL简单程序,有助于vhdl语言的初级学习!可以下载看看.-DDS program, contribute to the VHDL language primary learning! can be downloaded.
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
zhongji
- 基于vhdl的dds信号发生器程序，具有一致十k调频功能，输出32k及64k正弦波-Based on the dds signal generator vhdl program has a consistent ten k FM function, 32k and 64k sine wave output
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
sanjiaobo
- DDS信号源中关于三角波的设计，程序上采用VHDL编写，结果仿真通过-DDS signal source on the triangle wave design, procedural preparation of VHDL simulation results through
sin
- DDS信号源设计中关于正弦信号的波形发生器，采用VHDL编写完-DDS signal source design on the sinusoidal signal waveform generator, using VHDL prepared END
FSK
- 本程序用VHDL语言基于DDS的原理实现了FSK调制-This procedure using VHDL language is based on the principle of DDS achieve FSK modulation
dds_test
- 用来测试DDS程序的，使用的芯片是9854，语言为VHDL，里面含有测试结果图，对需要的朋友非常有用-DDS program used to test the chip using a 9854, language VHDL, which contains test results chart is very useful for a friend in need
AD9858_point
- DDS采用AD9858元器件，使用VHDL编写两点切换点频程序。-AD9858 DDS using components, the use of VHDL frequency switching point two procedures.
FIR
- 用VHDL写的FIR滤波器，前端有DDS产生波源-Write VHDL FIR filter, front end DDS generated wave source
delay
- VHDL代码，源用与两路DDS之间的相位差，现可用于产生相位差可编程的1m时钟，精度可精确到0.01分。输出两路时钟，带起始控制位-VHDL code, source with the phase difference between the two DDS, can now be used to produce 1m phase programmable clock accuracy can be accurate to 0.01 points. Output two clocks with
dds_
- 基于VHDL的DDS 串口控制 ROM 文件由MATLAB生成-dds using VHDL serial control
hdsdds
- 实现直接数字频率合成器，使用VHDL语言描述-DDS VHDL
mydds
- 通过VHDL编程，在FPGA内实现DDS模块生成正弦波-Through VHDL programming, within the FPGA to realize DDS module to generate sine wave
DDSN
- quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
dds_clk
- VHDL代码实现FPGA中DDS功能，输出频率可调-VHDL code for the FPGA DDS function, the output frequency is adjustable
DA1RefComp
- 基于xilinx开发环境 adc7303驱动程序，源代码以vhdl描述，实现数字信号到模拟信号的转换。可用于dds的波形输出。-The driver of adc7303 chip by using vhdl.
test3
- DDS 100MHZ to 4MHZ este DDS esta reado con ISE NAvigator en lenguage VHDL, funciona pero hay diferencias con la cantidad de muestras para crear la onda senoidal, se recomienda aunmentar el numero de muestras para lograr una mejor exactitud de la on
eda
- 直接数字频率 相位累加器 寄存器 lpm_rom(Based on VHDL+ FPGA design of the DDS signal has been through mode)