搜索资源列表
Hamming
- Hamming Encoder of 7bit in VHDL, Where it consists 3 parity bits and 4 data bits, then after it is being passed to decoder where it corrects, if their is any error and gives desired data as output. -Hamming Encoder of 7bit in VHDL, Where it consist
FPGA_Project
- To design fixed point to floating point encoder and experiment with simulation, synthesis and implementation features of the Xilinx Project navigator. Specifically, the objectives of this lab are: 1. To try out basic building blocks of VHDL beh
BCD-youxianbianma
- 优先编码器，通过VHDL语言实现BCD优先编码的功能-Priority encoder BCD priority encoder function through VHDL language
HD6409_encode
- 基于VHDL语言的HD4069曼彻斯特编码器实现-Based on VHDL HD4069 Manchester encoder implementation
BCH
- 此代码用VHDL实现BCH(57,44,6)编码器，属于信道编码的内容，此外采用Miggitt译码器实现译码功能。-This code BCH (57,44,6) encoder using VHDL, is a channel coding content, the addition Miggitt decoder decoding function.
Experiment
- 可编程逻辑器件VHDL实现的3线-8线译码器-VHDL 3-8 priority encoder decoder
FSK
- vhdl编写的FSK编码器与解码器，绝对可用，拿去用吧。 -the FSK encoder and decoder VHDL written, absolutely free, and take with you.
82be270ea751
- RS（255，239）编码器的VHDL语言源代码，希望能对大家有一定帮助-the code of the encoder of rs（255,239），hope can help you
EDA
- VHDL 交通灯 奇偶校验器 编码器，教学所用-VHDL traffic lights parity encoder, teaching
bcd_adder
- 用vhdl实现的bcd编码器，实现bcd编码，实验程序，已经调试成功-To bcd encoder vhdl to achieve the bcd coding, experimental procedures, debugging has been successful
t_encoder
- encoder file with VHDL code, encoder file with VHDL code e ncoder file with VHDL code-encoder file with VHDL code, encoder file with VHDL code encoder file with VHDL code encoder file with VHDL code
8b10b_encdec_latest.tar
- 8B10B encoder VHDL code
oc_mkjpeg_rev61_subsampling
- JPEG encoder USING vhdl CODE TO RUN FOR CHECKING THE IMAGE COMPRESSION
recursiveconvolutional
- This simple vhdl program of RSC encoder-This is simple vhdl program of RSC encoder
coder83
- 基于VHDL的8-3优先编码器模块，din0-din7八位二进制输入编码后输出三位编码结果。采用正逻辑设计，高电平有效。-8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
viterbi_1
- low power convolution encoder and Viterbi decoder using vhdl code
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
rs(63-45)
- 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
arm_FPGA
- 步进电机、直流电机PWM控制、伺服电机编码器解码vhdl程序-Stepper motor, PWM DC motor control, servo motor encoder decoder VHDL program