搜索资源列表
vhdl
- 3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
abs_code.rar
- 这是用CPLD开发的读取绝对式编码器反馈的信号的代码，读取电机的转子的绝对位置和判断转动方向对于电机控制很实用。,This is read by the CPLD Development absolute encoder feedback signal to the code, read the motor' s rotor position and to determine the absolute direction of rotation is very useful for mot
EnDatlightversion
- 海德汉绝对值编码器的ENDAT2.2协议代码，用于编码器数据的解码，然后把得到的数据传送给DSP处理，我们公司用于高精度伺服驱动器上。-Heidenhain encoder absolute agreement ENDAT2.2 code encoder data for decoding the data and then transmitted to the DSP processing, our company for high-precision servo drive.
16b20b_Encoder
- VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
count_plus_last
- 对电机的编码器输入的正交编码信号进行4倍频处理 ，生成一个新的计数脉冲 ，同时判断电机的转动方向，输出一个方向标志电平信号，从而可以让DSP知道电机的转速和方向。-On the motor encoder inputs of the quadrature encoder signals 4 octave treatment, generates a new pulse count and at the same time to determine the direction of motor r
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
JPEG2000
- jpeg 2000 encoder complete document
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
8b10b
- 8b_10b encoder/decoder
encoder
- vhdl的七段译码器-The Seven-Segment Decoder VHDL
crcm
- crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Manchester
- “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
coder
- 这是用VHDL语言编写的3-8编码器，可以看到程序简单可行-This is the language used VHDL encoder 3-8, we can see that the procedure is simple and feasible
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
dp_test
- 本程序是用VHDL语言编写的，其中包括并口通讯，DDS电机调速,编码器信号处理等，对研究这方面的工程人员有一定参考作用-This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain refe
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
rsenc
- this the code for reed solomon encoder of type 7,3. this is the main module program.-this is the code for reed solomon encoder of type 7,3. this is the main module program.
mult2
- this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
mult4
- this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder