搜索资源列表
hdb3_codedecode
- 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功-Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
ADPCM
- ADPCM ENCODER and DECODER
DE2_NET
- document is waveform file testing for any RLE encoder
BCH_HDL_ENCODER
- Syntetizable source code of VHDL BCH(1023,1013) encoder. This scheme used by DTMB standart and produce ten redundancy bit on 125 cycles because bus width of 8 bits.
PWM_QEI_miniauto_V3
- 基于cpld的电机编码器源程序，很实用，精品程序-Cpld motor encoder based on source code, very practical, excellent program
RS
- RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
convencode2
- 卷积码（2，1，3）编码过程。代码清晰简单，对应人民邮电版《通信原理》中卷积码编码过程-Convolutional code (2,1,3) encoder. Code is clear and straightforward, Telecommunications for the corresponding version of " Communication Principle" in the process of convolutional coding
RS3123
- Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its ra
123
- 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
rgb2ycrcb
- code for jpeg encoder part
robotic_arm
- An effort has been made to design a robot, which loads and unloads an object to the station depending on the request. The sensor connected to the robot will sense the request and initiate the correct sequence of operation. The robot under design has
rs_dec_enc_latest.tar
- RS encoder decoder on vhdl
ldpc_encoder_802_3an_latest.tar
- LDPC encoder in verilog
RSencFlash
- RS(255,239) encoder for NAND Flash controller
div63
- 可以对增量式编码器输出的AB相信号进行整数分频。有一个简单的通讯接口，可设定分频大小。 -Incremental encoder can output an integer number for AB believe frequency. There is a simple communication interface, can set the size frequency.
RS_DesignNote
- Reed-solomon decoder, encoder design note
Altera_IP_verilog
- Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
ADPCMEncoder
- ADPCM encoder with ICON, VIO, ILA, working on Xilinx ISE and chipscope.
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code