搜索资源列表
mc8051-IP
- VHDL 8051 IP, VHDL写的8051的IP核。-VHDL 8051 IP
IP-coreincluding-VHDL-and-Verilog
- 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
IP_CORE_4
- An example of using VHDL IP cores for the Spartan 3A Stater Kit
OneWireMaster
- 美信onewire总线IP core,带验证激励-MAXIM DS1WM Synthesizable 1-Wire Bus Master IP core.
c8051
- 51单片机，基于vhdl的ip核，这资料非常有用，结构性非常强，值得学习-51 microcontroller based vhdl ip core, this information is very useful, very strong structural worth learning。
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
sunset-vhdl
- 小精灵自爆：采用64*4位ip核并随机赋值作为地图信息，小精灵具有一定血量，可以在地图上面根据周围敌人（赋值为1)数量和自己血量选择是否进行自爆。-Elf blew: 64* 4 ip nuclear and random assignment as the map information, the elves have a certain amount of blood, the map above surrounding enemies (a value of 1) the number a
greth
- This driver supports GRETH 10/100 and GRETH 10/100/1G Ethernet MACs available in the GRLIB VHDL IP core library.
fir-ip-vhdl
- altera quartus fir ip核 vhdl程序 含测试文件-altera quartus fir ip nuclear vhdl program including test files
FIFO
- FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
mc8051_design
- 使用VHDL语言，实现C8051 IP Core(Use VHDL, Realize C8051 IP Core)
smg_IP
- 在DE 2开发板上，编写vhdl语言，建立8段数码管IP核，在nios ii中编写C语言程序，实现8段数码管数码有规律显示。(In the DE 2 development board, the preparation of VHDL language, the establishment of 8 sections of digital tube IP kernel, in Nios II written in C language program, to achieve the 8 sect
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
10419729vhdl对数
- 进行对数运算的IP核，可以计算以2，10，e为底的对数，最高可输入24bit宽度的数据。 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。(The IP kernel that performs logarithmic operations can compute data at the base of 2, 10, and E, with the highest input 24bit width. Written in AHDL language, can
test51_PLL
- VHDL How to use PLL-IP core microsemi project
test42_CoreABC
- VHDL How to use CoreABC-IP with uart microsemi project
divider
- a vhdl code for divide operation in fpga spartan6
i2c
- 这是基于altera avalon-MM总线的I2C IP核。利用VHDL语言编写。(This is an I2C IP core based on the altera avalon-MM bus. Using VHDL language.)