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sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
MC8051
- 摘要:分析了与标准8051 MCU 兼容的MC8051 IP 核结构原理与设计层次，详细论述了MC8051 IP 核的FPGA 实现与 应用方法。通过试验验证，其性能比标准8051 MCU 高，方便与系统其他模块的集成。在各种嵌入式系统和片上系统 中使用该IP 核具有重要意义。 关键词: 单片机； MC8051； IP 核； FPGA； VHDL-Abstract: This paper is compatible with standard 8051 MCU MC8051 IP c
s3en_tcp
- 基于spartan3e开发板的嵌入式EDK软件平台下的TCP/IP协议的网口程序-Embedded development board based on spartan3e EDK software platform for TCP/IP protocol network port procedures
udp_ip__core_latest.tar
- udp/ip stack for just streaming the data over IP video or audio vhdl code to run in vhdl
pwm
- 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
DDR
- HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
AUDIO
- TLV320AIC23B的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-TLV320AIC23B the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
IIC
- 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
pwm
- 用VHDL语言 描述 生成pwm的 IP核-Pwm using VHDL language to describe the generation of IP core
mylcdip
- lcd vhdl ip 核 挂接在 opb 总线上 可以完美实现 lcd 字符液晶的 驱动。-this is a vhdl lcd character ip core based on OPB （onchip periheral bus）
ug_vip
- Altera公司原版设计手册，关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores i
auk_udpipmac-v3.3.0.tar
- The Altera(R) UDP/IP function implements a hardware solution for the transmission and reception of UDP/IP encapsulated network traffic.
Altera_IP_verilog
- Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
LCD12864IP
- 12864的IP，在艾米电子工作室的nios开发板上可执行-12864 of the IP, in the electronic studio nios Amy executable development board
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
PWMcore
- 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.
VGA
- 应用VEROLOG HDL编写的VGA的IP核，可用于SOPC BUILDER中-the control of the i2c bus
HDMI
- HDMI IP。VHDL语言实现。附带测试pattern。-HDMI IP VHDL
00
- 用VHDL语言调用IP核，在ISE中实现三角波-VHDL IP core with the realization of the triangular wave is called