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lunwen
- 潘明海 刘英哲 于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Mingha
we
- 用VHDL写的5级流水线的回写阶段，绝对好用-Using VHDL written five stage pipeline write-back, absolutely easy to use
MANIK
- MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density ̶
NCO
- Numerically Controlled oscillator with with quadrature output and pipeline-Numerically Controlled oscillator with with quadrature output and pipeline
Cordic123
- for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
ORTHO_vhdl_pipeline
- orthogonal in pipeline vhdl proce-orthogonal in pipeline vhdl process
ARM_Core
- ARM 7，有三级流水线，对于初学流水线芯片设计的学生来说，是个很好的教例！-ARM 7, there are three lines, chip design pipeline for beginner students, is a very good teaching cases!
iir_pipe1
- IIR pipeline VHDL FPGA
CPU
- 使用VHDL语言实现了一个两级流水线的CPU，-VHDL language using a two-stage pipeline of the CPU,
cpu
- 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
CPUwithout-cache
- 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
mips-vhdl
- MIPS VHDL Microprocessor without Interlocked Pipeline Stages
add48
- 本历程时用vhdl实现对48位加法器的流水线设计，通过本程序可以了解流水线的设计方法，可以结合流水线的示意图度此程序。-The process of using vhdl 48-bit adder pipeline design, pipeline design can learn through this program, this program can be combined with the schematic diagram of the pipeline.
control
- The Pipeline SPIN model using VHDL
CPU-VHDL
- cpu pipeline processing