搜索资源列表
Source.rar
- PWM Verilog源代码，可以通过仿真测试,PWM Verilog source code, can be tested through simulation
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
FPGAdezizhixingSPWMboChengXu
- 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
SOPC_pwm_source
- 在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware descr iption HDL files and driver files
moter
- VHDL写的PWM发生器，仿真通过，波形基本完美，可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
an501_design_example
- PWM文件 用于CPLD，学习如何用VHDL语言写程序-PWM files for CPLD, learn how to write VHDL language program
cpldpwm
- cpld的PWM输出控制，初学cpld良好例程-CPLD output of PWM control, a good beginner routine CPLD
ctr_rev_160us
- pwm控制模块 使用过很多次-pwm control module to use many times
PWM_control_motor
- This a project about PWM. Application in motor speed control-This is a project about PWM. Application in motor speed control
pwm_source
- Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
EP1C3_12_1_2_MOTO
- 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
pwm
- counter for pwm in order to generate pulses for the module it is required to write a program for counter
pmw2ppm
- Vhdl code PPM to pwm converte
pwm_gen
- PWM _Generator VHDL code
pwmtest
- 拨码开关控制PWM的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
PWMtest
- PWM 转模拟信号 拨码开关控制 PWM 的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
1
- Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
pwm
- 适合初学者对PWM调制的学习，解释比较明确，由于来元于核心程序，功能强大-Enables the keyboard scan code in Verilog source code, clear for beginners Comments
PWM
- VHDL code for PWM Generator with Variable Duty Cycle