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virtex5
- Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is l
alu32
- 32 bit ALU design using VHDL code for Xilinx ISE Foundation
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
Xilinx-labs-manual
- a Xilinx lab manual which contains sample codes and programming techniques which are used by beginners to learn VHDL
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
xilinx
- it contils more vhdl codings and is very useful
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
spi_int
- realize spi interface vhdl code xilinx help ths help developers
xapp1022
- xilinx FPGA利用MET平台测试PCIe IP核的说明文档与源文件、-xilinx FPGA platform testing by MET PCIe IP core documentation and source files
IVK_DVI_DVI_Pass_Through_Demo
- Xilinx IVK demoboard 上DVI to DVI 範例程式源碼-Xilinx IVK example programs on the DVI to DVI pass through demo code
UART
- 串口VHDL程序，Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
UART
- xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
SPI-Flash
- 基于Xilinx-SPartan 3an FPGA 的与单片机 SPI 接口 参考设计-SPI interface base of Xilinx Spartan 3AN kid
Xilinx-ISE-Simulator-(ISim)-VHDL-Test-Bench-Tutor
- Xilinx ISE Simulator (ISim) VHDL Test Bench Tutorial
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
VHDL-Tutorial
- VHDL Tutorial Based on Xilinx Spartan 3 Starter Kit Board
vhdl
- 基于PicoBlaze的实时时钟设计。PicoBlaze是Xilinx的8位软核。采用汇编语言编写。-Uart real timer
FPGAmusicBox_gunKaragoz.net
- Simple music box using a Digilent Basys2 Xilinx Spartan 3E-100 FPGA.