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Plasma_Cpu_r10.tar
- Plasma CPU: VGA coded with C and VHDL in Xilinx FPGA
pwm_lights
- 这是一个利用脉冲信号点亮LED灯的VHDL代码示例，可以用在xilinx的FPGA上-VHDL code example, a pulse signal lights LED lights can be used in the FPGA on xilinx
xapp1015
- SDI接口的VHDL实现，XILINX官网的设计参考-SDI interface VHDL realize XILINX official website design reference
Xilinx_vga_games_design
- 经典的程序，用VHDL编写的游戏，俄罗斯方块，在赛灵思Spartan板子上测试成功-Classic procedures, written in VHDL game, Tetris, on the board of the Xilinx Spartan test
XS3S1000
- XILINX公司XC3S1000FGG456下的VHDL工程,主要完成AD采用以及和CPU的数据交换-XC3S1000FGG456 s program example
8-3-Encoder
- VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
BCD-ENCODER
- VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
BIN-ENCODER
- VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
N---Bit-Full-SUBSTRUCTURE
- VHDL program for “N Bit Substructure” behavioral design in Xilinx integrated software environment
PARITY-ENCODER
- VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second
proj1
- 在Xilinx的ISE下用VHDL实现的3-8线译码器。-In the Xilinx ISE implementation using VHDL 3-8 line decoder.
13.Anvyl_PmodAD1_Demo
- 用VHDL写的AD程序，使用与xilinx开发板。-Written using VHDL AD process, use and xilinx development board.
14.Anvyl_PmodDA2_Demo
- 用VHDL写的da程序，使用与xilinx开发板。-Da program written using VHDL, use and xilinx development board.
06.Anvyl_vga_Demo
- 用VHDL写的VGA程序，使用与xilinx开发板。-Written using VHDL VGA procedures, using xilinx development board.
03.Anvyl_KYPD_SEG_Demo
- 用VHDL写的KEY程序，使用与xilinx开发板。-KEY program written using VHDL, use and xilinx development board.
xapp386
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Mas
xapp348
- This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunne
VHDL_design
- 本综合实验包括节拍脉冲发生器、键盘扫描显示和八位二进制计数器三个模块。采用VHDL语言为硬件描述语言，Xilinx ISE 10.1作为开发平台，所开发的程序通过调试运行验证，初步实现了设计目标。-This includes comprehensive experimental beats pulse generator, display and keyboard scan eight binary counter three modules. Using VHDL as the hardwar
src
- SRC IMPLIMENTATION ON VHDL USING XILINX AND FPGA GIVES HIGH SECURITY IN DATA TRANSMISSION