搜索资源列表
Counter
- Counter in VHDL using Xilinx ISE
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
moore
- 状态机 基于xilinx ise硬件描述语言-moore VHDL
counter4
- 计数器 基于xilinx ise硬件描述语言-counter VHDL
ds840_v_scaler
- v scaler xilinx vhdl
ISE_lab1
- 基于Xilinx公司Spartan 3E fpga,实现入门工程的建立，波形仿真，及下载VHDL程序，以及简单门级电路的设计-Based on the Xilinx Spartan 3E fpga, to achieve the establishment introductory engineering, simulation waveforms, and download VHDL procedures, and simple gate-level circuit design
VGA.doc
- 用vhdl实现横竖彩条纹的显示，通过xilinx仿真软件生成bit文件，下载到fpga开发板上-Horizontal and vertical stripes using vhdl color display, generate bit file by xilinx simulation software, download it to fpga development board
ComplexMult
- xilinx 复数乘法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear complex multiplication vhdl language calling with test procedures
Divider
- xilinx 除法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear division calls including test procedures vhdl language
Piano
- 用VHDL写的，实现触摸屏电子琴的功能，可录音、放音，适用于赛灵思的板子。-Written using VHDL realize the function of touch-screen keyboard, recordable, playback for Xilinx board.
pacman_vhdl_xilinx
- VHDL version of Pacman. Intended to run under Spartan II over the Xess dev.board but easily portable to any other Xilinx platform. Contains full project with all bitmaps and sounds.
ac701-pcie-rdf0225-2013.2-c
- 赛灵思7系列开发板ac701，PCIE参考设计，VHDL/Verilog，开发环境Vivado-xilinx 7 series design Kit AC701 PCIe reference design. VHDL/Verilog, design environment Vivado
ball_game
- VHDL VGA 弹球游戏 基于Xilinx Spartan 3E的FPGA 通过VGA显示弹球游戏-VHDL VGA pinball game is based on Xilinx Spartan 3E FPGA pinball games via VGA display
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
powerlink
- powerlink 次站VHDL源码，可以实现4中不同的模式，基于xilinx平台。-powerlink slave VHDL sourcecode，which is based on Xilinx platform.
1540000000000031952_taxi
- 一个基于FPGA使用VHDL语言编译的出租车计价器，在Xilinx ISE环境下编译-An FPGA using VHDL language compiler taxi meter, compiled under Xilinx ISE environment
TouchPad
- 一个触摸屏打地鼠小游戏 ，利用VHDL实现，在Xilinx ISE环境下编译。-A touch-screen play hamster game, using the VHDL implementation, compiled under Xilinx ISE environment.
12_Lab3
- practical example using verilog and vhdl by xilinx
LFSR
- practical example using verilog and vhdl by xilinx