搜索资源列表
decode
- VHDL 语言实现的viterbi 译码的源程序。-The source of viterbi decoder based on vhdl。
total
- viterbi decoder for communication system
Conv_encodeaaViterbi_decode
- 卷积编码，QAM解调器的软比特信息输入viterbi译码器进行软判决译码。-Convolution coding, the soft bit information QAM demodulator input viterbi decoder and soft decision decoding.
viterbi27_sse
- viterbi decoder using sse intrinsics
ViterbiDec
- 802.11协议中规定的卷积码，以及相应的维特比译码matlab仿真程序。-Conventional coder and its viterbi decoder, which defined in 802.11 protocol.
ViterbiDecode
- Viterbi decoder for convolutional coding (133 171)
adsp-2191_viterbi_decoder
- ADSP-219x Viterbi Decoder.zip中的文件可部署1/2速率维特比解码器，输入为软判决输入-his directory contains an example ADSP-2191 single-core subroutine that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder.
viterbi1
- viterbi decoder 2/3 rate
viterbi_decoder
- trellis based hard viterbi decoder for conultional encoder with rate 1/2 and generator polynomial [13,15] with initial zero state
HW2_conl_viterbi_part_b_soft_com
- in this file the Viterbi Decoder for communication develop
Design_and_Implementation_of_Viterbi_Dec
- viterbi decoder research paper
Forward_Channel_simu_IS_95_standrd_sys
- This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (R
viterbi37
- onvolutional encoder and Viterbi decoder for K=7 rate=1/3 code
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA
bpsk_RC_filter_convolution
- BPSK Raised Cosine Filter Convolution encoder and viterbi decoder matlab simulink file
qpsk_convolution_Interleaver
- QPSK convolution encoder and viterbi decoder Interleaver matlab simulink file
EGC
- EQUAL GAIN COMBAINING in MATLAB SOFTWARE with VITERBI DECODER
TRANSMIT-BEAMFORMING
- TRANSMIT BEAMFORMING WITH MATLAB SOFTWARE and VITERBI DECODER
verilog
- VITERBI DECODER MODULE This module implements the FSM and instantiation of all the modules used for Viterbi decoding.
max
- ber of convolutional codes and viterbi decoder