搜索资源列表
Multiplier
- It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
PCI_t
- PCI 3.3V 設計指南 Xilinx Spartan-3-PCI 3.3V design guide Xilinx Spartan-3
Customising_PetaLinux
- A pristine PetaLinux tree only includes pre-configured platform support for Xilinx FPGA based prototype development boards. The user needs to add their platform into PetaLinux before it can be used to build firmware for their target device. Customi
Xilinx_ISE_Tutorial
- A brief but very useful tutorial for the Xilinx ISE.
DUC
- 基于软件无线电的SFF平台，采用Xilinx System Generator实现的数字上变频器-SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter
sdram_ver_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
FPGAyanlitu
- 烧录升级文件需要的FPGA下载线原理图 xilinx官方的下载线原理图，里面用了两个74hc125。并口，线路很简单-Burning files needed to upgrade FPGA download cable schematic diagram official xilinx download cable schematics, which used two 74hc125. Parallel, the line is very simple
afifo_0916
- 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
XilinxFPGA-SELECT-form
- Xilinx+FPGA选型速查表-Xilinx+ FPGA Selection Fact Sheet. . . . . .
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and t
c_xapp858
- 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the i
ddr_verilog_xilinx
- xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
tutorial
- 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
lcd
- lcd display on xilinx spartan 3e
sincos
- 正弦和余弦波在xilinx FPGA中的产生方法， 有look up table方法-Sine and cosine wave in xilinx FPGA in the production method, and a look up table method
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
ug230
- Xilinx Spartan 3E 实验板详细说明书-Xilinx Spartan 3E board experiments detailed descr iption