搜索资源列表
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
PCIe_DMA_Freeware
- Xilinx PCIe 带 DMA，烧入V5平台验证过的，内有pdf文档详细的教程，windows驱动和应用界面也在里面，全面的一目了然的资料-Xilinx PCIe with DMA, burning into the V5 platform, verified with a pdf document detailed tutorial, windows driver and application interfaces are inside, comprehensive informatio
sp605_pcie_x1_gen1_canuse
- xilinx 评估板sp605的PCIe的verilog源程序，已经经过调试。-failed to translate
Xilinx_sparten3E_communication
- 在Xilinx Spartan-3E的开发板中，实现键盘和VGA显示器的通信的源代码，与大家分享：,In the Xilinx Spartan-3E development board, the realization of the keyboard and VGA display the source code of communication to share with you:
SPARTAN-3PINOUTINFORMATION.zip
- xilinx spartan3各封装引脚信息,xilinx spartan3 information on the package pin
MATLAB_sg_IP.rar
- 使用MATLAB为System Generator for DSP创建IP,The use of MATLAB for System Generator for DSP to create IP
RS232.rar
- 基于Xilinx Spartan3E的RS232驱动，能够实现FPGA与PC得通信,Xilinx Spartan3E based on the RS232 driver, to achieve a FPGA and PC communication
cf_dpsk.rar
- 用VHDl语言写的一个DPSK的调制和解调程序，该程序可以实现相对相位调制解调。可以运行在xilinx ISE 或者是QuartusII下。 ,VHDl written in a language with DPSK modulation and demodulation process, the program can be achieved relative phase modulation and demodulation. Can be run on xilinx ISE or Qua
8b10b编解码
- 8b10b编解码，aurora协议，遵照xilinx官网文档-8b10b encoder and decoder, aurora protocol
uart_fpga4fun
- rs232通信代码，在自己的xilinx开发板上已验证通过-rs232 code with verilog has been verified
VgaSnake
- 贪吃蛇+vga显示。有暂停、继续功能。Xilinx开发-Snake+ vga display. Pause, continue to function. Xilinx development
DUC.rar
- 基于XILINX ISE下的数字上变频设计，其中用到了XILINX的乘法IP。已经通过工程实用，好用。,XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
Xilinx ISE
- 硬件设计工具。相对容易使用的、首屈一指的PLD设计环境 ！ ISE将先进的技术与灵活性、易使用性的图形界面结合在一起，不管您的经验如何，都让您在最短的时间，以最少的努力，达到最佳的硬件设计。
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
gsrd_7_1_2
- xilinx下的Gbit级通行参考设计，已经过本人验证-Gbit-class xilinx passage under the reference design, I have been to verify
Device-DNA-Reader
- 基于Xilinx FPGAD SPartan-3an开发板的 DNA Reader参考设计-DNA Reader Base on Xilinx FPGAD SPartan-3an kit
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
c_wp260
- 利用 Xilinx FPGA 和存储器接口 生成器简化存储器接口-Using Xilinx FPGA and the memory interface generator to simplify memory interface
MB_LOGIC_LV
- run labview programs on xilinx fpga boards