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VGA.doc
- 用vhdl实现横竖彩条纹的显示，通过xilinx仿真软件生成bit文件，下载到fpga开发板上-Horizontal and vertical stripes using vhdl color display, generate bit file by xilinx simulation software, download it to fpga development board
Mold-sixty-counter
- 基于FPGA的模六十计数器设计。在xilinx上运行。-FPGA-based design mold sixty counter. Runs on xilinx.
Greedy_snake
- 利用Xilinx ISE平台在FPGA实验板和VGA显示屏上完成简单的贪吃蛇游戏-Use Xilinx ISE platform to complete a simple Snake game on FPGA experimental board and VGA display
bmd_design
- 基于XILINX VC6LX550T FPGA开发的xapp1052即DMA传输验证程序，接口部分的管脚绑定可根据自身芯片型号进行修改-Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
filter_2d
- XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
evodem_mppt_son_hali_OK
- This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSI
pg054-7series-pcie
- 赛灵思 7系列pcie设计，官方参考资料-xilinx 7 series FPGA PCIe design， reference
testlcd
- how to write on the LCD screen of the SPARTAN 3E with FPGA of XILINX
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo
ball_game
- VHDL VGA 弹球游戏 基于Xilinx Spartan 3E的FPGA 通过VGA显示弹球游戏-VHDL VGA pinball game is based on Xilinx Spartan 3E FPGA pinball games via VGA display
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
piso1
- The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
TP_13_12_2013
- Un ensembles des applications réaliser sous SDK xilinx pour FPGA Spartan 3E
Ecar
- 基于FPGA的一个小游戏，在VGA上实现赛车游戏,开发版型号为ANVYL燧石，在Xilinx ISE环境下编译-An FPGA-based games, racing games on the realization VGA, Developer Edition model ANVYL flint, compiled under Xilinx ISE environment
1540000000000031952_taxi
- 一个基于FPGA使用VHDL语言编译的出租车计价器，在Xilinx ISE环境下编译-An FPGA using VHDL language compiler taxi meter, compiled under Xilinx ISE environment
SIG_CLK
- 四分频，四个相位的时钟输出，FPGA，vhdl，xilinx-Divided by four, four-phase clock output, FPGA, vhdl, xilinx
Taximeter
- 出租车计价器（其中包括分频模块，计程模块，计时模块，计费模块，显示模块以及顶层模块），基于Verilog HDL语言，开发板是FPGA(Sparten 6 LXS45),开发环境是Xilinx。-Taxi meter (including frequency module, the meter module, timing module, billing module, display module and top-level module), based on Verilog HDL lang