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UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
ConvCodeXilinx
- This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutional encoder in xilinx virtex-5
vmodcam-ref-vga-demo-12
- 通过fpga（注：xilinx公司的板子）从vmodcam取数据并用vga显示。-vmodcam ref vga demo
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
FPGALVDS
- FPGA差分转单端（xilinx）,操作介绍，从源码角度介绍-FPGA differential to single ended (Xilinx)
da_80m_10m
- AD9747测试Verilog测试程序,FPGA为xilinx的SP6-the test program of AD9747，FPGA IS SP6
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍，对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.
s6all
- spartan6 系列FPGA PIN文件 xilinx不提供现成的库 用于生成器件原理图库-spartan6 series FPGA PIN file xilinx does not provide ready-made libraries for generating devices Principle Gallery
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
inc_pid
- 基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set-Incremental PID FPGA-based design methodology
example_design
- 基于Xilinx最新的Virtex-7的存储器IP核的使用，verilog语言编写的所有源码。-Based on Xilinx latest Virtex-7 FPGA,all of the MIG IP code sources by Verilog language.
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
AD5300
- FPGA外部AD部分代码，FPGA芯片采用xilinx sptan3e 可以实现AD的采集-The FPGA external AD code, the FPGA chip using xilinx sptan3e can realize the collection of the AD
PS2
- FPGA外部PS2j键盘部分代码，FPGA芯片采用xilinx sptan3e 可以实现键盘与串口的通信-The FPGA external PS2j keyboard part of the code, the FPGA chip using xilinx sptan3e can realize the keyboard and a serial port communication
Rxd-new
- FPGA串口部分发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA与电脑的通信-FPGA serial sections to send code, the FPGA chip using xilinx sptan3e can implement on FPGA and computer communications
SPI
- FPGA SPI部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA的SPI的通信,用来控制外部74hc595-FPGA SPI part of the code, the FPGA chip using xilinx sptan3e can realize SPI communication, FPGA is used to control the external 74hc595 are needed
TXd_FIFO
- 用FPGA 串口通信发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA向通过max232电脑发送数据-The FPGA to send part of the code, serial communication, the FPGA chip using xilinx sptan3e can implement on FPGA send through max232 computer data
key
- 实现FPGA 按键控制部分代码，FPGA芯片采用xilinx sptan3e 可以实现按下按键后FPGA通过max232给电脑发送数据-Achieve FPGA button control part of the code, the FPGA chip using xilinx sptan3e can realize after press the button the FPGA through max232 send data to a computer
BH_Shi_jizhi_Out
- FPGA开发 VHDL语言 常用进制转换 基于Xilinx开发平台 ISE软件-VHDL language commonly used FPGA development hexadecimal conversion based on Xilinx ISE software development platform