搜索资源列表
XAPP868
- E1/T1时钟提取和恢复源码 是xilinx的IP源码-E1/T1 clock recover code,it is xilinx s IP code
xlinx_ise_excd1_edk_flash_program
- 这是一个网友向我提问如何实现EXCD1开发板的FLASH管理，我编写的一个Xilinx的EDK设计包括设计步骤说明，没有经过实际测试，希望在实际使用中有问题的网友与我讨论。谢谢！-This is a friends asked me how EXCD1 development board FLASH management, I prepared a Xilinx s EDK design and including the design steps that, without actual te
comp4
- 用verilog编了一个比较器，开发环境是xilinx ise10.1-Verilog compiled using a comparator, the development environment is the xilinx ise10.1
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
gate
- 用verilog编写，与或非门的演示程序，编程环境是xilinx ise10.1.-Prepared using verilog, or non-doors demo program with the programming environment is the xilinx ise10.1.
alu4bitsynthesizable
- its a 4 bit arithmetic nd logical unit code in verilog. the software which is used for it is xilinx
frequency
- 基于XILINX平台设计的数字频率计，在FPGA内部设计信号源，产生100KHz方波，板上数码管用于显示被测信号频率，并显示6位有效数字，实现对TTL电平的测试，测量精度为10Hz。-: The digital frequency meter based on XILINX development terrace generates 100 KHz square waves by a supply oscillator within FPGA. The nixietubes of the boa
ModelsimVHDLWatch
- This tutorial is a part of a series of tutorials provided by Xilinx to lead the user through the Xilinx FPGA Design Flow. This archive contains the necessary design files to perform the tutorial.-This tutorial is a part of a series of tutorials p
ModelsimVerilogWatch
- Stopwatch Design - ModelSim Vlog Tutorial Required Software: - Model Technology Modelsim 5.4a - Xilinx Development System 3.1i CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -Starts and stops the stoopwatch
QAM16_demo
- This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xil
OFDM_Security
- This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simul
A_digital_WaveformGenerator_and_Oscilloscope_based
- 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.T
virtex5
- Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is l
XilinxFPGA
- 可以很快学会使用xilinx开发环境ISE，是一个不错的初级入门文件。推荐。-the PDH can easy make u know the sample knowlege on FPGA software ISE.it is worthy reading.
xilinxhelp1
- this is xilinx help guide
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
workspace0823
- 这是我写的基于xilinx公司的virtex5版本fpga的network底层程序，其中是C语言与API混合编程，希望对用得着的兄弟有些帮助。-This is what I wrote based company virtex5 xilinx fpga of the network version of the underlying process, which is a mixture of C programming language and API, the brothers want t
ml510_bsb1_std_ip_ppc440
- 这是Xilinx公司FPGA的标准的基于PowerPC440的IP包底层驱动程序，标准的，很难得。-This is the standard Xilinx, FPGA-based IP packet PowerPC440 the underlying drivers, standard, hard to come by.
Mark-test
- This file is a project consisting of Mark containing all the project from a to z in vdhl code and works on fpga spartan xilinx board.
xapp132
- xilinx source code for the design of ppl which is available in xilinx spartan3e