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ConvCodeXilinx
- This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutional encoder in xilinx virtex-5
readme_xupv5board
- this is xilinx univeristy program
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
da_80m_10m
- AD9747测试Verilog测试程序,FPGA为xilinx的SP6-the test program of AD9747，FPGA IS SP6
memory_test_edk_14p7_2
- 基于FPGA的流水灯程序，使用XILINX FPGA实现，在XPS平台上编写。压缩包是整个源工程。-FPGA water lamps procedures based on XILINX, using FPGA implementation, written in XPS platform. Package is the source project.
Real-time User Adjustable Video Filtering
- Real-time User Adjustable Video Filtering aim is to create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet
2_ISE5.1i_manual_CPLD_v1.0
- Xilinx manual Install & how to use it. language is korean
2013-06-5
- xilinx 嵌入式开发的一个入门的例子，实现m l405开发板led的闪亮。对于初学者有很好的借鉴作用-Examples of embedded development xilinx an entry realize m l405 development board led flashes. For beginners there is a good reference
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
MVB_test
- 此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。-This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.
OLEDandmicroblaze_SDK
- OLED在microblaze SDK下的应用,此工程是建立在xilinx斯巴达6系列做的oled显示图片程序-OLED under microblaze SDK, this project is based on xilinx Spartan 6 series of OLED display images process
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
sp605_IBERT_rdf0036_13.3_c
- 此文件是用所需的时钟缓冲器岁设计示例顶部包装。用户逻辑可以在此包装和岁设计实例化。XILINX官方参考设计。-This file is an example top wrapper for the ibert design with the required clock buffers. User logic can be instantiated in this wrapper along with the ibert design.
06168353
- The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compressio
SPI
- FPGA SPI部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA的SPI的通信,用来控制外部74hc595-FPGA SPI part of the code, the FPGA chip using xilinx sptan3e can realize SPI communication, FPGA is used to control the external 74hc595 are needed
dcm_1202
- 本程序是基于Xilinx的FPGA编程，运用ip核进行时钟的管理，且有测试程序。适合FPGA初学者。 -This procedure is based on Xilinx FPGA programming, using ip core clock management, and there is the test program. FPGA for beginners.
fifo_1
- 本程序是基于Xilinx的FPGA简单代码编写，对fifo的ip核进行简单的配置，并通过仿真代码进行仿真观察fifo的特性，适用于FPGA初学者。-This procedure is based on Xilinx' s FPGA simple code written for the ip nuclear fifo simple configuration, and Simulation observed through simulation code fifo for FPGA beg