搜索资源列表
DDS
- DDS函数信号发生器，这是我在xilinx平台上实现的，可以产生不同频率，不同函数形式的函数信号。如三角波，方波等-DDS function generator, this is my on xilinx platform, can produce the function of different frequency signals.
16FFT
- Xilinx的16点傅里叶分析，内有详细说明-The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary compone
1024FFT
- Xilinx的1024点傅里叶分析，内有详细说明-The xFFT1024 fast Fourier transform (FFT) Core computes a 1024-point complex FFT. The input data is a vector of 1024 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary
nysa_sata_latest.tar
- The Xilinx CORE Generator™ is used to create a single-lane PCIe Endpoint Plus design. The generated PCIe system contains the PCIe endpoint plus block, GTP tiles, block RAMs, and clock and reset modules. The tutorial below shows how to create the
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
8-TFT_24
- 基于Xilinx Spartan6自制开发板实验，2.4存TFT屏静态刷新特定图片。如果要修改图片，请使用Matlab将图片生成*.coe格式，生成ROM加载。-Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is gene
vga256
- 本代码是用于Xilinx FPGA 开发板 开发实验的 vga256 verilog源代码 -This code is used for Xilinx FPGA development board developed experimental vga256 verilog source code
sp6ex16
- 该文件是一个基于xilinx spartan 6芯片实现了uart通信的源码程序-The document is based on xilinx spartan 6 chip implements the source program uart communication
vga2
- 本功能主要实现了VGA的显示，分辨率为1024*768，包内有制作好的coe文件存入rom，适合xilinx芯片-This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
zhuangtai
- 本程序实现了报文功能，在通信传输中经常会用到，使用芯片为xilinx，verilog语言编写-This program implements packets, in the communication transmission is often used, the use of chip xilinx, verilog language
DSP-with-FPGAs
- Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algo
RGMII
- 用xilinx芯片实现千兆网的实例代码，您可以通过修改此代码完成基于ETMAC IP核的MAC设计，驱动外部PHY芯片或进行MAC to MAC 的直连通信设计。-this is code of etmac IP inst.. it will help you developing for MAC and PHY
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
pwm-generators
- 此程序的功能是基于xilinx公司ISE平台实现pwm发生器。-Function of this program is to achieve pwm generator based company ISE xilinx platform.
New-WinRAR-archive
- This program is of 8 bit full adder on xilinx also tested on cadence tool
New-WinRAR-archive
- This file for 4 bit up down counter tested on xilinx and cadence-This is file for 4 bit up down counter tested on xilinx and cadence
LED_bak
- LED流水灯，已经在xilinx开发板试验可行。-LED light water, has been in xilinx development board test is feasible.
xintf-fpga
- 本程序主要是实现xinlinx fpga与dsp之间的双工通信-This program is to achieve duplex communication between xilinx fpga and dsp
XC3S400TQ144
- Just little program for xilinx FPGA. It is can be used as a example for education.
project-main-doc
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is