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vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
ukwvf
- xilinx virtex fpga 这是一个用来检测局域网是否正常的程序的源代码(Xilinx virtex fpga whether this is a used to detect local area network (LAN) normal program source code)
AN84868 - Source files for FX3 Firmware
- 通过Cypress的EZ-USB FX3的SPI接口对Xilinx FPGA进行配置(AN84868 shows you how to configure a Xilinx FPGA over a slave serial interface using FX3 which is the next-generation USB 3.0 peripheral controller.)
idwt
- Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
XilinxVirtualCable-master
- Xilinx虚拟连接，这是一种基于TCP/IP协议的通信技术，以实现JTAG功能，通过这样的连接，可以访问开发的FPGA或者SOC，而不需要通过传统的JTAG电缆。(Xilinx Virtual Cable (XVC) is a TCP/IP-based communication protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design wi
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
sim_Xilinx综合与仿真设计指导
- Xilinx自己出的仿真设计指导，使用vivado工具必备参考资料。(The Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable Gate Array devices using a Hardware Descr iption language. It includes design hints for the novice HDL user, as w
pll_test
- PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource
pg058-blk-mem-gen
- blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
gtx_aurora_zc706_example
- Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enabl
ug835-vivado-tcl-commands
- Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s
HARLEQUIN_XC95288XL_REV_A_SCH
- This is document containing the schema of the Spectrum Harlequin A diff xilinx
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be
PipelineCPU
- 1. understand how to improve CPU performance 2. master the working principle of pipelined MIPS microprocessor. 3. understand the concept of data adventure, control risk and the solution of pipeline conflict. 4. mastering the testing method of pipe
RotaryEncoder
- 基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)
microblaze实例教程
- 一般而言，Xilinx Microblaze会被用来在系统中做一些控制类和简单接口的辅助性工作，比如运行IIC、SPI、UART之类的低速接口驱动，对FPGA逻辑功能模块初始化配置及做些辅助计算等等。类程序的代码量普遍不大，常常在十几KB到几时KB之间，因此对存储的需求通常也不是太高，使用FPGA内部RAM资源便已经够用(Generally speaking, Xilinx Microblaze will be used to do some auxiliary work of control
xapp870
- sata物理层 ，实现物理层的参考，可以借鉴一下(phy layer for sata,target is Xilinx ML505 .)