搜索资源列表
opb_ethernetlite
- The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3 Media Independent Interface (MII) specification, which should be used as the definitive specification. Differences bet
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
dividefreq
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
This_is_pci-wishbone_nuclear_and_16450_serial_port
- 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
video_capture_rev_1_1
- 视频图像的捕捉系统的实现，主要是基于XILINX系统的实现-Video image capture system implementation is mainly based on XILINX System
picieee.tar
- The Synthetic PIC is a synthesizable VHDL descr iption of the basic Microchip PIC 16C5X microcontroller. It is written in the ViewLogic VHDL environment (Workview PLUS 5.2). It has successfully been synthesized to the XC4000 family, although
spartan6_fpga_CLB_guide
- xilinx FPGA的CLB高效设计，对提升设计质量很有用-xilinx FPGA' s CLB efficient design, to enhance the quality of design is useful
DDRIO
- Xilinx公司开发板中的一个模块，在时钟的上升和下降沿同时传输数据。使用时需要在ISE集成开发环境下利用VHDL进行例化。本文是对该模块功能的说明，是个人的学习总结-Xilinx has developed a module board, in the clock' s rising and falling at the same time transmission of data. ISE needs to use integrated development environment
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
ispdown
- 能够支持多种芯片下载，如：at89单片机，arm单片机，xilinx等芯片的下载。共能强大-Able to support a variety of chip download, such as: at89 microcontroller, arm microcontroller, xilinx chips and other downloads. A total is strong! !
high_speed_data_recovery
- 1. 程序的功能是:高速串行数据的恢复. 2. 其基本原理是：利用过采样，检测串行数据的边沿跳变，然后根据边沿提取处在数据相位正中央相邻的抽样值，将串行数据恢复过来。 3. 此程序是verilog 语言编写，用于xilinx virtexE 系列的FPGA-1. Program functions are: high-speed serial data recovery. 2. The basic principle is: the use of over-sampling to det
Rocket
- 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and st
CSC_XAPP931_pdf
- This document is Xilinx`s Color Space Conversion Applcation Note. This CSC is a RGB to YCrCb Conversion.
Synthesis_and_Simulation_Design_Guide
- xilinx的综合与仿真设计指导书，内容基础，讲解细致，比较可惜的是资料是英文的。-xilinx synthesis and simulation design guide book, the content-based to explain detailed comparison is a pity that the information is in English.
lab1
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第一部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the first part of the tutorial
lab2
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第二部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the second part of the tutorial
lab3
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第三部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the third part of the tutorial
lab4
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第四部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the fourth part of the tutorial
lab5
- 经典嵌入式EDK设计教程，使用的是XILINX公司的EDK开发软件。这是教程的第五部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the fifth part of the tutorial