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code_lock_vhdl
- 在ISE环境下用vhdl写的一个密码锁程序。下载到xilinx 公司的 spartan6 的板子上验证过的，也有仿真代码。主要就是几个状态之间的转换，用了一个moore状态机。-In the ISE environment using vhdl to write a lock program. Downloaded to the board spartan6 xilinx' s proven, there are simulation code. Mainly the conversion
car
- 基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器-Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
led_shift
- 在xilinx的ISE上写的LED灯移动的verilog程序-a verilog code for led-shifting which writed with ise 14.2
i2c_lightsensor
- 用Verilog HDL编写的光敏传感器AD/DA程序，AD结果显示在LCD上，DA结果控制LED的亮度，相关软件：ISE Design suit，硬件：xilinx FPGA开发板-Verilog HDL prepared with light sensors AD/DA program, AD results are displayed on LCD, DA of controlling LED brightness, software: ISE Design suit, hardware:
pwm-generators
- 此程序的功能是基于xilinx公司ISE平台实现pwm发生器。-Function of this program is to achieve pwm generator based company ISE xilinx platform.
digital-frequency
- 简易数字频率计设计，使用ise软件仿真，xilinx芯片，可以测输入信号的频率-Simple digital frequency meter design, simulation ise software, xilinx chip that can measure the frequency of the input signal
Seven_segment_display
- SEVEN SEGMENT DISPLAY, ON VHDL, ISE DESIGN SUITE 14.7, XILINX
dwt
- Running: C:\Xilinx_Installed\14.3\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -pr
szmb
- 用VHDL语言基于ISE，在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
Verilog HDL program
- 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and
variable_duty_cycle_pwm
- VHDL project in ISE Xilinx for PWM generation
xilinx_lib.tar
- 用于modelsim仿真的xilinxfpga平台IP库，以ise 13.x为基础制作，在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
35_OV7725_VGA_DDR3_LX16_joint
- 多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
ug835-vivado-tcl-commands
- Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s
dds
- dds算法，调用xilinx IP ，ise(DDS algorithm, call Xilinx IP, ISE)
SN7474
- 74LS74芯片行为级代码，实现了双D触发器与逻辑延迟，可利用modelsim仿真(74LS74 chip behavior level code)