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Nfenping
- 通过硬件描述语言VHDL编写的任意模小于1024的N分频器，思路简单，用计数的原来实现，通过波形仿真的源代码（波形仿真文件）含-Through the descr iption of the written language VHDL hardware mold is less than 1024 arbitrary N prescaler, ideas, with simple, through the original count of simulation code (waveform w
frequency
- 在CPLD和FPGA上采用VHDL语言进行分频器设计，供设计者参考-digital frequency divider design with VHDL
divtest
- VHDL数字锁相环所用的分频器，需要的同学可以试一下。-fenpinqi
songer
- 根据给出的乘法器逻辑原理图及其各模块的VHDL描述，学习利用数控分频器设计硬件乐曲演奏电路-According to the logic given multiplier module schematic and its VHDL descr iption, learning to use the numerical design of the hardware musical performances divider circuit
example1
- div 分频器 自己用vhdl语言写的 比较简单-div vhdl design
fen_pin
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -fen pin
music
- 功能描述：向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状态机和分频器使蜂鸣器发出"多来咪发梭拉西多"的音调。（VHDL）-Function Descr iption: to the buzzer to send a certain frequency square wave can make the appropriate buzzer tone, the experiment by designing a state machine and the divider
8fen
- 8分频器的VHDL源码，绝对正确，并且可根据本代码推导出各个2的幂数的分频器的编写原理。-FDCT Frequency Divider by VHDL .
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
gmsk_2
- 实现2M数据速率的GMSK调制，时钟频率20M，2分频后作为移位寄存器-2M data rate to achieve the GMSK modulation, the clock frequency of 20M, 2 minutes after a shift register frequency
traffic
- 采用VHDL语言编写的控制交通灯工作的程序。分为四个部分：1，分频器，2，计数并产生控制信号，3，交通灯信号产生，4，交通灯总体描述。点击lzh6.aws打开工作空间-VHDL language used to control traffic lights work procedures. Divided into four parts: 1, divider, 2, count and generates control signals, 3, traffic signal generatio
frediv
- EDA分频器代码vhdl例程，可用，方便理解-EDA divider vhdl code routines that can be used to facilitate the understanding of
fenpin2500
- 用VHDL写的分频器,分频大小为2500分频-Written with VHDL divider, size frequency frequency 2500
NCDividerAndItsApplicationVHDLSourceeCode
- 用VHDL编写的数控分频器及其仿真结果图片。该程序能实现PWM波形输出以及产生正负脉冲宽度可调的方波输出。-Prepared by the NC VHDL Simulation results divider and pictures. The program can achieve positive and negative PWM waveform output and pulse width adjustable square wave output.
frediv
- 1:1占空比的分频器的VHDL实现，包括奇数和偶数分频。-1:1 duty cycle of the divider of the VHDL implementation, including the odd and even frequency.
VHDLFPQ
- VHDL(分频器),包括奇数分频和 偶数分频，等等常用语句-无
50MSeparatefrequencydevice
- vhdl语言设计中常用到的50M分频器，可以以此设计出各种需要的分频器。-vhdl language commonly used in design to the 50M divider, can also be used to design the divider needs.
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
miaobiao
- 用VHDL实现的秒表功能，包括分频器，动态显示模块-VHDL implementation with stopwatch functions, including crossover, dynamic display module